Coupling & Crosstalk: Roller Coasters & Proverbs

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2020 edition on pages 9-10.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Roller Coasters & Proverbs

Are you the type of person who flips to the end of the book to see how the story ends before starting it? Or one who reads the online reviews with the plot summary – including the spoilers – before watching the movie? If so, do you want to know how the coronavirus COVID-19 epidemic turns out? Continue reading “Coupling & Crosstalk: Roller Coasters & Proverbs”

Coupling & Crosstalk: Trust your Paranoia!

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2019 edition on pages 11-12.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Trust Your Paranoia!

President Ronald Reagan’s use of the Russian proverb “Doveryai, no proveryai was the perfect soundbite to describe the 1987 Intermediate-Range Nuclear Forces Treaty. What does this and Andy Grove’s “only the paranoid survive” have to do with semiconductors? Continue reading “Coupling & Crosstalk: Trust your Paranoia!”

Coupling & Crosstalk: KGD Redux?

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2019 edition on pages 9-10.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

KGD Redux?

Known Good Die (KGD) – Is this a case of “everything old is new again” or acid reflux from a mature semiconductor industry?  Today there is a greater need than ever to know that a given semiconductor die is good before proceeding to package it.  This particular quest for the holy grail has provided plenty of Continue reading “Coupling & Crosstalk: KGD Redux?”

Coupling & Crosstalk: 5 Thoughts About 5G

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2019 edition on pages 9-10.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

5 Thoughts About 5G

1 – Just in time.  The cell phone has Continue reading “Coupling & Crosstalk: 5 Thoughts About 5G”

Coupling & Crosstalk: Look beyond the small screen to get the big picture!

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2019 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Look beyond the small screen to get the big picture!

The electronics industry is in a transition forced by rapid changes in computer hardware and concepts. However, there is even more change on the horizon and this historical perspective can help you to understand and plan for the future.

The earliest ‘big iron’ computer systems were built to solve Continue reading “Coupling & Crosstalk: Look beyond the small screen to get the big picture!”

Coupling & Crosstalk: Knowledge worker or knowledge serf?

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the 
Winter 2018 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Knowledge worker or knowledge serf?

“I want to chat with you but first I need a few moments to finish a computer task I’m working on. Rats! Why doesn’t it work? Hmm, the last time I did this was a year ago. Nothing seems the same, I first must untangle my brain from what appears to be non-standard logic and useless updates.”

Have you tried to figure out how you did something last time by Continue reading “Coupling & Crosstalk: Knowledge worker or knowledge serf?”

Coupling & Crosstalk: Milking It!

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2018 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Milking It!

I observed recently two different companies “milking” their businesses for good and for ill. With the proper perspective, consumers can see how well an organization manages and cares for their products – tangible goods and services. Not just in the headline news which may be indicative outliers (airline mistreatment of passengers, anyone?) but in everyday interactions and purchases.

What does milking a business – be it cows or dishwashers – have to do with high technology? Continue reading “Coupling & Crosstalk: Milking It!”

Coupling & Crosstalk: Project Management – What me worry?

Courtesy of Mr. Murphy!

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2018 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Project Management – What me worry?

Alfred E Neuman’s famous “What me worry?” quote should always be in your thoughts at the optimistic beginning of any project. As reality kicks in and the project grinds on-and-on you will finally start remembering Andy Rooney’s somber, pragmatic quotes.  Project success will depend on your team’s ability to Continue reading “Coupling & Crosstalk: Project Management – What me worry?”

Coupling & Crosstalk: Testing the Supply Chain

change canstockphoto28381385_focalpoint_c350x350 Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2018 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Testing the Supply Chain

Much the same as the world, test is not simply black or white but varying shades of grey and a jumble of colors. Test has continually responded to semiconductor technology challenges to provide the right solutions. As a result, the organizational placement and “supply chains” for test have rarely been Continue reading “Coupling & Crosstalk: Testing the Supply Chain”

Coupling & Crosstalk: 1, 2, 3, 4 … 5G – Ready in 2020?

5G canstockphoto22241792_300x200Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2017 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

1, 2, 3, 4 … 5G – Ready in 2020?

Everyone loves a spectacle: the Olympics have become a marketer’s dream, shining a spotlight on new products for a world-wide audience. It is no wonder we have been promised demonstrations of “5G” cellular technology at the 2018 Winter Games (South Korea) and 2020 Summer Games (Japan). While there is going to be an inordinate amount of “hoopla” surrounding 5G, Continue reading “Coupling & Crosstalk: 1, 2, 3, 4 … 5G – Ready in 2020?”

Coupling & Crosstalk: “We are on fire!” – Good News, Bad News, or Both?

on_fire_canstockphoto44691393_300x240Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2017 edition on pages 7-8.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

“We are on fire!” – Good News, Bad News, or Both?

When a business is said to be on fire does strategy go out the window? It is curious that fire or fire-related terms are used to characterize two extreme states of business. A business on fire may think they are like a professional athlete Continue reading “Coupling & Crosstalk: “We are on fire!” – Good News, Bad News, or Both?”

Coupling & Crosstalk: Smoke and Mirrors? A Failure in Three Acts

credit card house of cards canstockphoto22380257_250x250Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2017 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Smoke and Mirrors? A Failure in Three Acts

Wow, that’s cool and I really want one! In fact it is a perfect solution to _______. Those are typically my first Continue reading “Coupling & Crosstalk: Smoke and Mirrors? A Failure in Three Acts”

Coupling & Crosstalk: Quality, Meet Safety & Security!

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2016 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Quality, Meet Safety & Security!

What can be simpler to specify or install than a light bulb controlled by a wall switch? Over-engineered versions, especially when developed without engineers, can really cause you to lose sleep. However, the real nightmare is the danger of Continue reading “Coupling & Crosstalk: Quality, Meet Safety & Security!”

Coupling & Crosstalk: Avoiding Ruts and Nuts!

ruts-canstockphoto9368594_450x300Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2016 edition on page 8.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Avoiding Ruts and Nuts!

We just completed a fantastic trans-Canadian family road trip! The highlights included Glacier National Park in Montana along with Banff & Jasper National Parks in the Canadian Rocky Mountains. The trip provided the right amount of “disconnecting” both physically, (or should I say wirelessly?), and mentally. During this time I observed a number of ruts of the repetitious, not the sexual Continue reading “Coupling & Crosstalk: Avoiding Ruts and Nuts!”

Coupling & Crosstalk: Moore Has Left the Building!

Dollars-Electronics canstockphoto8813445 Geleol 300x330Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2016 edition on pages 12-13.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Moore has Left the Building!

Unlike Elvis, Gordon Moore, the co-founder of Intel, is still with us. Although the debate continues among very smart people as to whether Moore’s Law is “truly dead”, this argument is now purely academic. As the electronics industry has moved to the “Post Personal Computer (PC) Era”, Moore’s Law which accurately predicted price over time for complementary metal–oxide–semiconductor (CMOS) integrated circuits, is no longer relevant.

Heresy! Did he just say that Moore’s Law doesn’t matter? Continue reading “Coupling & Crosstalk: Moore Has Left the Building!”

Coupling & Crosstalk: Engineering: The Solution to Software Quality!

house of cards canstockphoto10105769 200x300Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2015 edition on pages 11-12.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Engineering: The Solution to Software Quality!

Who is an engineer? In a recent Atlantic article, “Programmers: Stop Calling Yourselves Engineers”, Ian Bogost argues strongly that software developers should not be called engineers based upon several factors including quality, professional licensure, and liability. Mr. Bogost includes examples of where software has failed even as it has become critical infrastructure. Having struck a nerve, there are several notable rebuttal articles and thousands of comments on the original article.

But instead of arguing over who should be called an Engineer Continue reading “Coupling & Crosstalk: Engineering: The Solution to Software Quality!”

Coupling & Crosstalk: Headlines, trend lines, or expertise?

Shanghai Oriental Pearl Radio & TV Tower
Shanghai Oriental Pearl Radio & TV Tower
 
Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2015 edition on pages 10-11.

 
Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Headlines, trend lines, or expertise?

The recent stock market sell-off caused significant emotional distress to many investors who were caught off-guard. Looking past “the sky is falling” headlines, what business lessons Continue reading “Coupling & Crosstalk: Headlines, trend lines, or expertise?”

Coupling & Crosstalk: Over Connected?

Apple-Watch-Shinya_Suzuki_flickr17078894786_ec2467b9e6_o_crop_600x551Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2015 edition on pages 11-12.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Over Connected?

I’m torn. Should I buy an Apple Watch? Is this an ego trip or clearly a left versus right brain decision? Regular readers of my column know how much I appreciate Jony Ive’s designs and that Apple generally does an excellent job of both engineering and marketing. However, those who are familiar with my work and personality know Continue reading “Coupling & Crosstalk: Over Connected?”

Semiconductor Wafer Test Workshop 2015 Presentation – Are You Really Going To Package That?

Are You Really Going To Package That? - Ira Feldman and Debbora Ahlgren - SW Test 2015
Click image to download presentation

I had the pleasure of presenting “Are You Really Going To Package That?” at the 25th annual Semiconductor Wafer Test Workshop (SW Test / SWTW) on Tuesday June 9, 2015. Debbora Ahlgren and I took this opportunity to step back and look at how old paradigms in test-cell integration may lead to suboptimal solutions.

In an effort to reduce the cost-of-test (COT), a number of customers are increasing the parallelism of logic wafer probe cards. However, due to the complexity such as pitch and number of probes, the pricing for these cards is reaching astronomical levels. We do not believe this trend is sustainable, let alone logical. The presentation suggested examples of alternative solutions. It is clear that critical solutions need to be optimized at the test cell, factory, and supply chain level not just at the consumable (probe card) level.

Coupling & Crosstalk: Products or Services?

products-services-canstockphoto10272610-300x300Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2015 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Products or Services?

Paper or Plastic?” A simple grocery store inquiry? Think again: this decision has many layers of complexity as does the examination of products versus services. There have been endless discussions as to the benefits and downsides of paper, versus plastic, bags. Everything from environmental concerns, to reusability, to biodegradability, and much more has been deliberated. Just when we thought that the paper bag had Continue reading “Coupling & Crosstalk: Products or Services?”

Coupling & Crosstalk: First World Problems

hurdles-canstockphoto10553904 800x475Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2014 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

 

First World Problems

Returning home with a carload of food for our Thanksgiving feast, we discovered our garage refrigerator had died. The only appropriate response other than panic was to Continue reading “Coupling & Crosstalk: First World Problems”

Trillion Sensors – TApps: Ultra-High Volume Sensor Applications for Global Challenges

Click image to download presentation
Click image to download San Diego TSensors Summit presentation (update of Munich)

 
It was my pleasure to organize and present at two TSensors Summits: Munich and San Diego this fall. The enthusiasm and intellectual “horsepower” of the presenters and attendees was incredible!

My presentations explain Continue reading “Trillion Sensors – TApps: Ultra-High Volume Sensor Applications for Global Challenges”

Coupling and Crosstalk: Medically Deficient Technology

hosptial canstockphoto16671639 600x400
Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2014 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

 

Medically Deficient Technology

It has been a very challenging month helping my best friend who has been in an intensive care unit (ICU) following a stroke. It has been very difficult emotionally seeing him incapacitated as he makes a slow recovery with many ups and downs.

As expected, in a top-rated Silicon Valley hospital, technology abounds and permeates all aspects of patient care. However, I’ve observed many examples where Continue reading “Coupling and Crosstalk: Medically Deficient Technology”

Coupling & Crosstalk: MVP for Hardware Development?

feature box canstockphoto15992543 300x341Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2014 edition on page 8.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

MVP for Hardware Development?

Just like professional sports leagues, lean product management has MVPs! Sports teams try out players, compete, and then end the season with “Most Valuable Players” and champions. Unlike sports, winning product managers start out with Minimum Viable Products (MVPs) early on to Continue reading “Coupling & Crosstalk: MVP for Hardware Development?”

IEEE Semiconductor Wafer Test Workshop 2014 Presentation

International Technology Roadmap for Semiconductors (ITRS) - Ira Feldman - IEEE SWTW2014
Click image to download presentation

At the 24th annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) on Wednesday June 11, 2014,
I had the pleasure of presenting “International Technology Roadmap for Semiconductors”. This presentation was co-authored with Dave Armstrong (Advantest) and Marc Loranger (FormFactor).

For the last fifteen years the International Technology Roadmap for Semiconductors (ITRS) has been looking fifteen years into the future. Based upon technology requirements and other inputs, ranging from the gate size of transistors to advanced packaging technology, the Test and Test Equipment Technical Working Group (Test TWG) has worked to develop the requirements for test technology and equipment.

The Test TWG is over seventy volunteers with deep technical expertise in test from around the world and from every sized company – Fortune 100 to individual consultants – and every type of company – semiconductor independent device manufacturer (IDM), fabless semiconductor, foundry, outsourced assembly and test (OSAT), automated test equipment (ATE) suppliers, prober, probe card, socket, handler, and more. Through Continue reading “IEEE Semiconductor Wafer Test Workshop 2014 Presentation”

Coupling & Crosstalk: Disposable Chips?

cups plates forks canstockphoto2604892 250x345Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2014 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Disposable Chips?

I’m not a fan of disposable cups and other tableware. Yes, they are convenient and in some cases even economical. However, they are not great substitutes for Continue reading “Coupling & Crosstalk: Disposable Chips?”

BiTS Workshop – The Next 15 Years

Thanks to the BiTS Committee for the hard work to make this a great event!
Thanks to the BiTS Committee for the hard work to make this a great event!

Wow! The Burn-in and Test Strategy (BiTS) Workshop just turned 15! The world of semiconductors has certainly changed over the years. And the BiTS Workshop has kept up with what is “Now & Next” in the burn-in and test of packaged integrated circuits (ICs). These achievements were celebrated in style by the more than three hundred participants at the recently held 2014 BiTS Workshop in Mesa, Arizona.

“When the BiTS Workshop started in 2000, there were no Continue reading “BiTS Workshop – The Next 15 Years”

SEMI ISS 2014 – Scaling Innovation

Courtesy of Ivo Bolsens (Xilinx), SEMI ISS 2014
Courtesy of Ivo Bolsens (Xilinx), SEMI ISS 2014

Don’t pop the champagne just yet! Although plenty of good news was shared at the 2014 SEMI Industry Strategy Symposium (ISS) there was the sobering outlook of possible limited long-term growth due to technology issues as well as economic projections. Noticeable was the lack of news and updates on key industry developments.

This is the yearly “data rich” or “data overload” (take your pick) conference of semiconductor supply chain executives. The majority of the attendees and presenters are from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. Keeping the pressure on for advanced technology were the “end customer” attendees and presenters – semi-conductor manufacturers.

The official theme was “Pervasive Computing – An Enabler for Future Growth” and the presentations made it clear  Continue reading “SEMI ISS 2014 – Scaling Innovation”

Coupling & Crosstalk: A Trillion Sensors?

Janusz Bryzek's TSensor Vision
Janusz Bryzek’s TSensor Vision

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2014 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Name Calling

Whatever you desire “there’s an app for that!” Dream big or small, it is very likely a software program is already available. But what if you dream in hardware?  Hewlett-Packard is building applications with one MILLION sensors. Robert Bosch is dreaming of 1,000 sensors per person, i.e. seven TRILLION. Janusz Bryzek is aiming for one TRILLION per year.

Standardized smartphone hardware platforms and application “stores” have significantly lowered the cost and time to develop and sell applications. One might argue Continue reading “Coupling & Crosstalk: A Trillion Sensors?”

Chip Scale Review: The Three Most Important Words for 3D ICs?

Source: Bryan Black (AMD)
Source: Bryan Black (AMD)

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Continue reading “Chip Scale Review: The Three Most Important Words for 3D ICs?”

Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!

IWLPC_logo

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Market adoption is increasing rapidly for wafer level packaging (WLP) as it is applied to a greater range of applications. The shift of “Post-PC” from desktop to mobile devices has driven the development of WLP into the mainstream by providing extremely space efficient and low cost packaging. There has and will continue to be many technical and business challenges in packaging devices on wafer (or other substrate) en masse instead of on an individual basis.

Similar to wafer level packaging technology itself, the 2013 International Wafer-Level Packaging Conference (IWLPC) Continue reading “Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!”

Coupling & Crosstalk: Priorities First! Or Last? Or Not At All?

pina colada - canstockphoto1826026
 Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2013 edition on page 12.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

 

Priorities First! Or Last? Or Not At All?

Do I confuse being busy with being productive?

Does being efficient help me reach my goals?

What should my goals be?

Maybe I’m too much of a management geek since I spend my “lazy” summer days thinking about these topics instead of working on my tan.  Okay, truth be told Continue reading “Coupling & Crosstalk: Priorities First! Or Last? Or Not At All?”

Coupling & Crosstalk: Name Calling

good bad dice canstockphoto9654181 250x320Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2013 edition on pages 13-14.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Name Calling

What’s in a name? A lot! A name itself might not mean much but it can trigger expectations and stereotypes. In the United States we have red states and blue states depending on which political party has the majority vote. Similarly, when someone labels themselves on the basis of their political party affiliation (Republican, Democrat, Libertarian, Independent, etc.) others Continue reading “Coupling & Crosstalk: Name Calling”

IEEE Semiconductor Wafer Test Workshop 2013

Ideal 3D Stacked Die Test - Ira Feldman - IEEE SWTW2013
Click image to download presentation

I had the pleasure of presenting “Ideal 3D Stacked Die Test” in Session Two “Industry Trends and Advanced Packaging Challenges” of the 23rd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) on Monday June 10, 2013.

Integrated circuits using 2.5D advanced packaging are shipping. 3D packaging with thru-silicon vias (TSV) has been demonstrated. “5.5D” packages may not be far behind. Probe card suppliers have made progress building interconnect technology for the micro-bump arrays. Standards committees have started defining IC interface standards and test access protocols.

But what does the Test Engineer and Management really want? What can they afford? What are the most likely scenarios? Factors that determine which test technology can support the desired test flow are examined. In particular, probe card technology for probing TSV bumps and potential usage models are reviewed.

Coupling & Crosstalk: Measuring Up

bathroom scaleCoupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2013 edition on page 14-15.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Measuring Up

Tap to turn on. Wait for it to zero. Step on. I haven’t lost any weight, still 205 pounds even with all this exercise and careful eating? Step off, step back on. 212 pounds. Damn, wrong answer. Step off, step back on. 206 pounds. Okay maybe the first reading was right. Optimistically record 205 pounds. Does this nightly dance sound familiar? Not only are bathroom scales the bearer of bad news, their Continue reading “Coupling & Crosstalk: Measuring Up”

Riding Off Into the Sunset – BiTS 2013

Sunset over Phoenix, Arizona during BiTS Workshop
Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Continue reading “Riding Off Into the Sunset – BiTS 2013”

SEMI ISS: Sense of Scale

Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013
Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013

Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.

The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.

The whiplash comes from  Continue reading “SEMI ISS: Sense of Scale”

Feldman Engineering 2012 Wrap Up

2012

As we bid adieu to 2012, I realize that I have been remiss in providing updates on all of the exciting activity since my last one in May. I will rectify this situation below and have added regular updates to my list of New Year’s resolutions.

Challenges

In May, it was great to see the many responses to the Big Hairy Audacious Goal where Janusz Bryzek (Fairchild Semiconductor) challenged the microelectromechanical systems (MEMS) industry at the MEMS Technology Symposium that I described in “Thinking Big: $1 Trillion MEMS Market” (part 1 and part 2). 

In June, I reviewed the test challenges of the transition to 450 mm semiconductor wafers with my presentation “The Road to 450 mm Semiconductor Wafers” at the IEEE Semiconductor Wafer Test Workshop (SWTW). I have posted summaries of this entire excellent workshop: keynote and sessions 1, 2, 3, 4, 5, 6, 7, 8, and 9.

In one very hectic July week, I attended the summer working meeting of the International Technology Roadmap for Semiconductors (ITRS), the SEMICON West trade show, and the Test Vision 2020 conference. The focus of  Continue reading “Feldman Engineering 2012 Wrap Up”

Coupling & Crosstalk: Quality for the Long Haul?

Quality SealCoupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2012 edition on page 12-13.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Quality for the Long Haul?

Does a manufacturer’s responsibility and interest in quality end when the warranty expires?

When is death premature? People have life expectations based upon family and societal statistics as well as their health. Mechanical devices, especially those with moving parts, have estimated lives and known wear out mechanisms. Cars currently have an average age of 11 to 13 years of useful life which allows consumers to set reasonable expectations of service life. What about electronics? What is a reasonable expectation of service life?

I had a few devices at home fail recently which makes me wonder about Continue reading “Coupling & Crosstalk: Quality for the Long Haul?”

Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

Lego Blocks (flickr: antpaniagua)
Lego Blocks (flickr: antpaniagua)

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span Continue reading “Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging”

MEMS Testing and Reliability 2012 – Session 4

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

 

Session 4

Mervi Paulasto-Kröckel (Professor, Aalto University) in “On the Reliability Characterization of MEMS Devices” examined the current methods for reliability assessment in MEMS devices and identified necessary improvements. Currently, the reliability of MEMS devices are evaluated in the functioning state. A sensor is tested by applying a known stimulus and comparing the sensor output while varying the test conditions such as temperature, humidity, etc. MEMS actuators are similarly tested by providing a known input and measuring the output of the actuator over the range of test conditions. Significant deviation between the expected and measured result indicates a failure. Simple functional test is appropriate for manufacturing quality testing however it is inadequate for measuring and improving device reliability.

Professor Paulasto-Kröckel compared these processes commonly used to estimate MEMS reliability to those used in the microelectronics industry. She identified major methodology changes required  Continue reading “MEMS Testing and Reliability 2012 – Session 4”

MEMS Testing and Reliability 2012 – Session 3

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

 

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren’t really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of Continue reading “MEMS Testing and Reliability 2012 – Session 3”

MEMS Testing and Reliability 2012 – Session 2

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 2

Mårten Vrånes (Director of Consulting Services, MEMS Journal) in “A Test-centric Approach to MEMS ASIC Development” discussed alternatives to the traditional co-design of the MEMS element and application specific integrated circuit (ASIC). As many MEMS devices require an ASIC to control and/or sense the MEMS element the most logical approach is to design both parts in parallel. However the scope of such a development effort is often beyond the resources – both in terms of talent and funding – for many companies especially startups.

Mr. Vrånes started with the challenges and pitfalls of ASIC development for MEMS devices. There are challenges regardless of Continue reading “MEMS Testing and Reliability 2012 – Session 2”

MEMS Testing and Reliability 2012 – Session 1

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960’s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960’s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include Continue reading “MEMS Testing and Reliability 2012 – Session 1”

LinkedIn Lady Radio Show: Marketing & Social Media Applications


Not enough time to plan, execute, and measure the ROI of the marketing for your business? Hey, there’s an app for that!

I was pleased to be Ken Herron’s guest on the October 24 edition of the LinkedIn Lady radio show. We had a great discussion about marketing and social media applications.

To hear the show:
   via iTunes
   download a MP3 file

 

Please send me your questions in the comments below or feel free to contact me directly if I can help your business!

Here is the show announcement:

As an independent consultant, Ira works with his high technology clients to move their products from concepts to commercialization. Marketing is an area of expertise in which he assists his clients, who range from solopreneurs to large publicly traded companies. At the same time, he markets his consulting services to his own customers. In this show, Ken and Ira will discuss marketing for small businesses. They will talk about marketing strategy, channel selection, and content optimization, which are even more important for business owners with limited time and resources. Ira and Ken will discuss all of the major social channels, including: Facebook, Twitter, LinkedIn, Pinterest, Instagram, YouTube, and Slideshare, and the latest free tools to help YOU get the most out of your social marketing efforts to grow your business.

Join Ira and Ken on your computer or smartphone on the Wednesday, October 24 LinkedIn Lady radio show at 4:00 p.m. Eastern / 1:00 p.m. Pacific. Only on the LinkedIn Lady radio show on the Rock Star Radio Network!

Coupling & Crosstalk: Painting Lessons

Joseph and Della Ready to Paint

Coupling & Crosstalk is my new column in the MEPTEC Report. This column appears in the Fall 2012 edition on page 10.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions like this one may deliver a message closer to home!

Painting Lessons

It is time for our nine-year old twins to have their own bedrooms. The first step was to paint the rooms since the last time they were painted was well over ten years ago. Throughout the process I was reminded of many management and life lessons. Is this a worthwhile do-it-yourself (DIY) project? Does this first question set off the alarm bells? Can you Continue reading “Coupling & Crosstalk: Painting Lessons”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)

Here are the highlights from Session Six “Meet the Challenge” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Robert Stampahar (SV Probe ‐ An Ellipsiz Company) and Wally Haley (Qualcomm), “Meeting the 1st Silicon: An Alternate Approach for Reducing Probe Card Cycles”:

Unlike other devices which can be tested in packaged form using a test socket, wafer level chip scale packages (WLCSP) rely completely on wafer probe cards for test. A load board with a test socket can usually be designed and fabricated quickly enough that the bring up and debug of new silicon designs is not delayed. When using a wafer probe card that contains a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer, the delivery of the probe card is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

Click image to download presentation

Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paperThe Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)

Semiconductor wafer test workshop swtw sign

Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:

Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]

Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)

Semiconductor wafer test workshop swtw sign

Here are the highlights from Session Two “Optimizing Probe Depth Performance” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Tommie Berry (FormFactor, Inc.), “Actual vs. Programmed Over Travel for Advanced Probe Cards”:

As the number of probes on a probe card increase, the total force required to compress these probes – know as probe force – is increasing. With high force the actual over travel (AOT) – also know as overdrive – of the probe is often significantly different than the programmed over travel (POT) programmed in the prober. Even though memory test engineers with very high probe count cards have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

Semiconductor Wafer Test Workshop SWTW banner

This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons:  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

Thinking Big: $1 Trillion MEMS Market – Part 2

Part 1 described Janusz Bryzek‘s ambitious goal of a $1 trillion market for microelectromechanical systems (MEMS) that was the focus of the MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium. In addition, sensor swarms, road mapping and market numbers were covered. Challenges, example applications, and key takeaways are discussed here along with a final score card on the $1 T market.

Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 2”

Thinking Big: $1 Trillion MEMS Market – Part 1

Usual business advice includes thinking big to win big. Some organizations create Big Hairy Audacious Goals. Others like to find new markets that are underserved and grow to be number one. The semiconductor industry has Moore’s Law – the premise that the minimum cost point is achieved by doubling the number of transistors per chip every two years – driving it forward for almost fifty years.

Janusz Bryzek set a dramatic and ambitious goal of $1 trillion sales for the microelectromechanical systems (MEMS) market in 2022. Even though the MEMS market is expected to have “only” $12 billion in revenue in 2012, he isn’t being called a fool. Having cofounded eight seminal Silicon Valley MEMS companies and currently the Vice President of MEMS Development at Fairchild Semiconductor (which recently acquired his last company), Janusz is taken quite seriously.

Yes, at last week’s MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium there were some who  Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 1”

Green on the Industrial Scale

Molecular Layer Deposition of Polymers – George, Yoon & Dameron [4]

Many exotic materials or materials with special properties are processed using extreme temperature and pressure often with toxic starting materials. In semiconductors, molecular beam epitaxy (MBE) to build single crystal structures and sputtering are common methods of physical deposition to deposit thin films. Both are done using a very high vacuum. MBE heats the atomic materials until they sublimate and land on the desired surface. Sputtering uses a gas plasma to knock a few atoms of material off a “target” and onto the desired surface. There are also different chemical deposition processes including electroplating which uses metal salts dissolved in a solution bath, chemical vapor deposition (CVD) which uses high vacuum, and atomic layer deposition (ALD) which is similar to CVD but uses two half-reactions of gas phase precursors

Limitations imposed by extreme temperature, extreme pressure, and toxic materials combined with a typically slow deposition rate make it is difficult to economically run these processes on an industrial scale for high volume manufacturing. But what if there was a process that  Continue reading “Green on the Industrial Scale”

The Importance of Fundamentals

Joseph and Della Ready for Ski Lessons

While working with our son Joseph on his homework and skiing earlier this year, I was reminded of the importance of fundamentals. The challenges may have seemed an epic struggle from his perspective as an eight year old. As an adult, I was better able to put them in the proper perspective. Upon reflection on the seemingly unconnected events, I find they are both important reminders about learning and life in general.

Like other children and some adults, Joseph was having difficulties with math. He was struggling with his third grade homework Continue reading “The Importance of Fundamentals”

Change the Rules to Win!

Some consider the many of billions of dollars invested in the semiconductor supply chain to be huge bets on yet to be proven technology and future business. Even if you take a strict view of this as simply business it is possible to learn something from gambling.

The Atlantic tells the fascinating story of how Don Johnson took Atlantic City casinos for $15 M playing blackjack. Last year he won $5 M from Borgata in February, $4 M from Caesars in March, and $6 M from Tropicana in April. This wasn’t luck and he wasn’t card counting. How did he do this and how does this connect to semiconductors and Apple?

Continue reading “Change the Rules to Win!”

Memory Technology – Off to the Races!

Speed and Power

If we were focused on just these two parameters, we could be talking about horses, cars, or airplanes. But throw in density, endurance, and price and it is a horse race of different color. Not only does the winning technology have to balance speed and power, it needs to pack more functionality per area at a lower cost than existing solutions. Along with the endurance to last ten or more years.

With annual revenues once exceeding $60 B and now running $45 B due to dropping demand and prices, the global market for semiconductor memory is an exciting race. It is hard to believe that NAND Flash has grown to Continue reading “Memory Technology – Off to the Races!”

Two Conferences – Two Industries Challenged By Post PC Era

Tim Cook introducing Apple's latest iPad

The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.

Even though many were surprised to learn that we are now “Post PC”, some of us who have been developing strategies for the electronic supply chain have Continue reading “Two Conferences – Two Industries Challenged By Post PC Era”

Customer Service – the Good, the Bad, and the Ugly

Le client n’a jamais tort – César Ritz (1850-1918)

Fastest Way to Lose Customers - click for full infographic

Regardless of language or adage used, customers are the lifeblood of any business. Without customers, there is no business. How is it that businesses lose sight of this? Sometimes customers are taken for granted and are not part of a company’s core values. Other times, as organizations and processes grow in complexity they loose sight of the customer. And quite often teams don’t take sufficient time to look at themselves from the customer’s perspective.

As shown in the infographic above, it is really about the customer experience if 68% of lost customers leave due to poor treatment. It doesn’t matter whether your product or service is consumer focused (groceries, clothing, electronics, medical, legal advice, etc.) or industrial (semiconductor capital equipment, wafer test probe cards, nuclear power plants, etc.). The only difference may be Continue reading “Customer Service – the Good, the Bad, and the Ugly”

SEMI ISS – Snapshot of a Wild Ride – Other Coverage

Michael Splinter (Applied Materials) - Relative industry cost improvements and volumes.

I hope that my summaries of the first day of SEMI Industry Strategy Symposium (ISS) 2012 in

provided useful insights to the economic roller coaster that is the semiconductor market and its equipment and material supply chain. There have also been several good reports Continue reading “SEMI ISS – Snapshot of a Wild Ride – Other Coverage”

SEMI ISS – Snapshot of a Wild Ride – Session 2

After a gloomy first session focused on world economics at SEMI Industry Strategy Symposium (ISS) 2012, Session 2 – Semiconductor Markets was significantly more upbeat.

Stephen G. Newberry (Vice Chairman of the Board,  Lam Research Corporation) started off with a way forward in Continue reading “SEMI ISS – Snapshot of a Wild Ride – Session 2”

SEMI ISS – Snapshot of a Wild Ride – Session 1

Like the roller coaster ride that is the semiconductor industry, the SEMI Industry Strategy Symposium (ISS) 2012 had its share of ups, downs, twists, and turns. Semiconductor Equipment and Materials International – better known as SEMI – as the industry association of suppliers to semiconductor manufacturers has held this annual conference in early January for thirty five years to provide updates on business conditions and technology roadmaps to enable SEMI members to plan for the coming year. The conference was packed with senior management paying close attention to the industry leaders, analysts, and customer presenters. All of the presentations, even the most poorly disguised sales pitch or infomercial, contained several valuable insights.

In his keynote presentation “Technology Law Still Delivers“, William Holt (Senior Vice President; General Manager, Technology & Manufacturing Group, Intel Corporation) opened the conference with much optimism based upon Continue reading “SEMI ISS – Snapshot of a Wild Ride – Session 1”

Big Numbers – The Semiconductor Supply Chain

…To make sense of the big picture, one needs to follow the money and then head to China.

Ed Pausa the primary author of PricewaterhouseCooper’s (PwC) recently published report “Continued Growth: China’s Impact on the Semiconductor Industry – 2011 Update” provided an overview at this month’s MEPTEC luncheon. His presentation was a helpful tour to start digesting this impressive report, now it its seventh annual update. The report runs 112 pages in length and is packed with figures, data and most importantly analysis. Building a cohesive picture from many disparate data sources is a major undertaking and PwC should be applauded for making available this excellent work.

After listening to this presentation and reading the report, I find two items that really stand out as primary market forces. Unraveling the convoluted web of the semiconductor supply chain to examine these items will lead to greater understanding of the industry. They are, Continue reading “Big Numbers – The Semiconductor Supply Chain”

Think Outside the Box in 2012!

Joseph and Della in a box

At this time of year, when my children see a box arrive they immediately question if it is another present for them. They are very disappointed when the Amazon.com box contains breakfast cereal or dish detergent. They are definitely thinking inside the box. If the box is large enough, they will eventually start playing in it and imagine it is not a box.

Childrens’ imagination has no bounds. Adults need to make conscious efforts to think outside the box as this can Continue reading “Think Outside the Box in 2012!”

Silicon Valley Test Workshop – 2nd Year “Rocks”

2 5D? 3D? What? 3D IC Packaging - Ira Feldman
Click image to download presentation

Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Continue reading “Silicon Valley Test Workshop – 2nd Year “Rocks””

Semiconductor Packaging: 2.5D, 3D, and Beyond!

MEPTEC's 2.5D, 3D and Beyond Packaging Conference

The MEPTEC2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.

Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with Continue reading “Semiconductor Packaging: 2.5D, 3D, and Beyond!”

Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers

Lessons for MEMS Test Engineers
Click image to download presentation

The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.

My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.

I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.

With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.

IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

 

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Continue reading “IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Seenew Lai, MPI,High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:

The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined Continue reading “IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)

Semiconductor Wafer Test Workshop SWTW banner

Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Kevin Fredriksen, SPA GmbH, MSO – Multi-Site Optimizer”:

Most wafer probers do not supply intelligent stepping algorithms to calculate the most efficient sequence of moving the wafer relative to the probe card. (Ed: At the core of this is a traveling salesman problem.) The situation is exacerbated when Continue reading “IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)

Semiconductor Wafer Test Workshop (SWTW) Banner

Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:

Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.

The IBM team adapted a burn-in board system to Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Spring Pin Probing – Session Five (Tuesday)

Semiconductor Wafer Test Workshop (SWTW) Banner

Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:

Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Continue reading “IEEE Semiconductor Wafer Test Workshop – Spring Pin Probing – Session Five (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)

Semiconductor Wafer Test Workshop (SWTW) Banner

Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:

Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Continue reading “IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)”

IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

Semiconductor Wafer Test Workshop (SWTW) Banner

Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are Continue reading “IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)”

IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”

IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)

Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:

Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.

One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.

Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)”

IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)

On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.

Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:

Dr. Chen started with Continue reading “IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)”

Probe Card Cost Drivers from Architecture to Zero Defects

Click image to download presentation

As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.

Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.

Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.

There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.

I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.

 

IEEE Nanotechnology Symposium – Session 1 – Energy Generation and Storage

US Energy Flow 2009 (LLNL)

Here are the highlights from Session 1 – Energy Generation and Storage of the recent IEEE San Francisco Bay Area Nanotechnology Council Symposium:

Dr. Dania Ghantous, V.P. Technology of Qnovo: “Lithium-Ion Batteries: Opportunities and Challenges”

Dr. Ghantous provided an overview of lithium-Ion (Li-ion) battery technology and market since Qnovo is still in “stealth mode”. She did say that battery life, charge time, and cost are Continue reading “IEEE Nanotechnology Symposium – Session 1 – Energy Generation and Storage”

IEEE Nanotechnology Symposium 2011 – Keynote

Dr. Narayan
The IEEE San Francisco Bay Area Nanotechnology Council held their 7th annual symposium this week. As in the past, the council presents an excellent program. This year’s program focused was “Nanotechnology – Consumer Applications.”

Here are my notes from the keynote presentation by Dr. Spike Narayan, Functional Manager IBM, “Nanotechnology: Leveraging Semiconductor Technologies to Address Global Challenges.”

He asks: can we leverage semiconductor technology to address global challenges of environment, energy, healthcare, and water? Others have made a compelling argument that Continue reading “IEEE Nanotechnology Symposium 2011 – Keynote”

iPad Memories

…or Memory Magic via More Than Moore

Toshiba 16 Die Stack (64 GB NAND Flash)

No this isn’t a soliloquy to an Apple iPad that is no longer, but a brief tour of the incredible memory, packaging, and system technology that can be found under the hoods of the original iPad and the iPad 2 along with some of the manufacturing and test implications. These devices clearly demonstrate the new paradigm of “More Than Moore where scaling of systems and packaging will propel the next wave of growth in electronics beyond the traditional doubling of performance every two years predicted by Moore’s Law. For many in semiconductor packaging and test engineering communities the issues related to More than Moore have been an academic discussion up to now, but clearly the success of the iPad product line shows the current reality for advanced devices and where the future is headed. Apple and their suppliers took huge risks in developing these new technologies in exchange for substantial returns.

As I recently noted in “Memory Alphabet Soup“, the most pressing question about memory most consumers currently have is “which iPad 2?” – 16 GB, 32 GB, or 64 GB? If Mr. Jobs believed in Continue reading “iPad Memories”

Memory Alphabet Soup

iSuppli Flash Market Forecast (Jan 2011)

There are so many different types of memory technologies that there is an alphabet soup of acronyms. Ever wonder why we have many different memory technologies some long forgotten with more on the horizon? I refreshed my own memory after last week’s IEEE Nano Technology Council presentation on conductive bridge random access memory (CBRAM).

 

The simple answer is Continue reading “Memory Alphabet Soup”

Yes, 40%, Most Likely

What does your model say?

What does your model predict?

Even though this sounds like the start of a Carnac the Magnificent comedy act, these are some of the answers from my Probe Card Market model. I keep my model current so I know both industry and company specific performance as well as to make predictions. You don’t have a model? Are you reacting instead of predicting?

So here are the “questions” being answered:

Continue reading “Yes, 40%, Most Likely”

Data Exhaust & Data Waves

Is your team reacting or predicting?

Last week, I heard Paul Kedrosky, Senior Fellow at the Kauffman Foundation and Bloomberg contributor, present “Data Exhaust: What We Know About Everything By What No One Tells Us” at the PARC Forum. “Data Exhaust” is his term for the “unintended information we throw off in our daily activities”.

His primary example was the analysis of the debris reported in real time by the California Highway Patrol (CHP). He found patterns that were temporal (Christmas trees in early December and late January) and geographic (mattresses near a discount mattress store immediately adjacent to an on-ramp thereby lacking the opportunity to determine if the mattress was secure prior to driving at speed). More strikingly he discovered the number of ladders dropped on Southern California freeways coincided with Continue reading “Data Exhaust & Data Waves”

Preparing to Succeed

Two fatal management extremes:
“Analysis Paralysis” and “Just Do It”

Analysis Paralysis” – over-analyzing the situation resulting in no action – prevents progress when overly detailed plans are made. It can be caused by corporate culture (no action = no criticism of possible failure), budget restraints (study costs are minimal; action costs are major), and/or no confidence in the outcome.

Just Do It“, the other extreme, may be the response to a protracted case of analysis paralysis or “full speed ahead” management style. Regardless of the cause, proper preparation is often neglected especially when budget and/or time are constrained.

What is the proper balance between the two? How does one change default behavior?

Continue reading “Preparing to Succeed”

Happy Holidays!

Lake Tahoe
From the snow of the Sierras to the sands of the Pacific we’re blessed in California to choose our scenery for the holidays. These grandeurs pale in comparison to the company of family and friends.
La Selva Beach (Santa Cruz County)

May you and your family be blessed with health and prosperity in 2011!

Silicon Valley Test Conference – Something New & Overdue

Starting off something new is often challenging and difficult with many unknowns. Kudos to Nick Langston for creating the Silicon Valley Test Conference that was held last week. (November 8 & 9, 2010) It was the first test conference to actually take place in Silicon Valley. And yes there were some minor “bugs” like registration delays and a no-show by the audio visual contractor that should be solved in next year’s Rev 2.0. Even with a few rough edges, the quality of the presentations and the exhibitors shined through to make this a success.

The conference opened with an excellent keynote address by well-known industry expert Continue reading “Silicon Valley Test Conference – Something New & Overdue”

MEMS Technology Summit – Day One – AM (2)

CardioMEMS EndoSure Wireless Pressure Sensor

From the MEMS Technology Summit at Stanford University, here are the highlights from the second morning session on Tuesday October 19, 2010:

Professor Thomas Kenny, Stanford University, Keynote: “MEMS Goes Mainstream, but Where are We Going?”

  • What are we trying to do? Make money – others will cover that topic – and to enable capabilities. But we need to look at how well we have achieved this.
  • Nanotechnology promises are un-fulfilled: There has been lots of hype and promises in the literature for over ten years. But what we are missing is the “technology” side of Nanotechnology. Perhaps Nanotechnology is an oxymoron? Continue reading “MEMS Technology Summit – Day One – AM (2)”

MEMS Technology Summit – Day One – AM (1) – Special Presentations

MEMS Products Phases of Development - Yole Research
Last Tuesday,the MEMS Technology Summit at Stanford University, opened with a welcome by Professor Roger Howe. Roger not only provided a brief history of MEMS at Stanford, he was his characteristic gracious self and welcomed even those with close ties to Berkeley especially the Berkeley Sensor and Actuator Center (BSAC). Truth-be-told even though Roger is a Mudder first, Continue reading “MEMS Technology Summit – Day One – AM (1) – Special Presentations”

WOW! MEMS Technology Summit

Having just completed a very busy two and half days at the MEMS Technology Summit at Stanford University, my lasting impression is “WOW”! The conference really did live up to their theme “Lessons from the Past and Vision for the Future”.

From the pre-conference tour of the Linac Coherent Light Source at SLAC National Accelerator Lab to the presentations by the best and brightest in the MEMS industry to the closing reception this evening, there was no end to information, interaction and networking, all of the highest quality. As part of the theme, the conference celebrated Continue reading “WOW! MEMS Technology Summit”

How to re-FORM or refill a fab

Fill 'er Up To Make Money

I usually try to ignore items that are unattributed, however a recent blog posting in the ElectroIQ blog “How To Fix FORM” caught my attention. It is true that FormFactor’s current difficulties are being discussed widely. However, the simplistic analysis and suggestions of this unknown “industry insider” need a reality check. The writer gets some of the overall problems right but may be missing the boat on the solutions.

Here are the supposed anonymous industry insider’s suggested fixes:

Continue reading “How to re-FORM or refill a fab”

Recovering from (our) Recession

… Not for the squeamish or faint of heart.

A few days ago, I attended the Keizai Society’s panel presentation “Recovering from Recession“. The panelists did an excellent job in interpreting the current economic data and both the short and long term issues. In addition, they cited lessons learned from Japan’s Lost Decade and how it applies to our current situation. The good news is we did learn a lot from their Lost Decade and other recessions; the bad news is that things are going to look gloomy for some time!

Dr. Daniel Okimoto, a Stanford University professor, who is Director Emeritus, Shorenstein Asia-Pacific Research Center (APARC) started the evening. Even though many of the issues he raised were not “new-news”, Dr. Okimoto did an excellent job of putting them in perspective to describe the current situation.

Here are highlights of his presentation followed by some of my own analysis:

Continue reading “Recovering from (our) Recession”

SolFocus: Focused on System Economics

At Tuesday’s IEEE Nanotechnology Forum, Phil Metz, Director of Business Development for SolFocus, discussed their technology in his presentation “SolFocus Concentrator Photovoltaics – An Introduction“. Though I enjoyed learning about their concentrator photovoltaic (CPV) technology (the presentation was appropriately focused for the audience), I had a greater appreciation for their integrated system approach including the economics. This was evident in the non-technical details he shared. As an early adopter with a residential photovoltaic (PV) system, I was surprised when comparing systems beyond the core technology.

Both CPV and PV systems convert the energy radiated from the sun to direct current (DC) power. Most “grid tie” systems then use an inverter to convert the DC power to alternating current (AC) power which is then fed into the power grid. Beyond these basic similarities, there are large differences in technology, complexity, and economics between the systems.

Continue reading “SolFocus: Focused on System Economics”

The night my computers died…

Electrical Receptacle Wall Plug AC Outlet Ground Tester
Got one?

And how I became intimate with my water heater.

Suddenly, all the computers in my office fell silent but strangely the room lights were still on. After initial panic and bewilderment, I was able to solve the mystery and was again reminded of the value of standards and budgeting to do it right from the beginning (pay now to avoid paying more later).

Even though I did not immediately respond by formally establishing a structured problem solving methodology with an eight step discipline (or other QMS variant), my engineering background intuitively guided me through a similar process. This was also a reminder that troubleshooting very simple systems without advanced preparation can be fairly complex and time consuming, therefore proactive preparation for complex systems is essential.

Continue reading “The night my computers died…”

Beware the Cost of Complexity

Early in my career in Hewlett-Packard manufacturing, we did a study that showed that the greater the configuration options we put on a single product the higher the cost to produce every other product in the same factory. Known as “Cost of Complexity” this has been found in many different industries with examples from software coding, to network support to food production. Not to mention in our own products, companies, and everyday lives.

Continue reading “Beware the Cost of Complexity”

Probe Cards & Dart Boards

The wildly varying projections for the semiconductor market in general and the wafer probe market in specific makes me believe that many analysts are simply torn between reporting their tea leaf readings and the scores on their dartboard. A hopefully more reliable source is VLSI Research and their annual probe market survey is eagerly anticipated every spring. One may argue about methodology but on the whole they do an excellent job of painting a comprehensive picture.

Their optimistic forecast is heartening but increased sales volume doesn’t always translate into profits and downturns when they occur can be fatal. Do you prepare for growth like a hare or a tortoise? Do you build excess capacity (“Field of Dreams“), take and fulfill new orders with lots of overtime and temporary workers, or do you forgo new business that bears high incremental start-up costs?

Continue reading “Probe Cards & Dart Boards”

Shinkansen =”Train Envy”

The California High-Speed Rail Authority made the news after their monthly public meeting last Thursday in San Francisco. They rotate cities throughout the state each month to obtain a wider range of public input. And the Bay Area didn’t fail to deliver, especially on the contentious issue of how the trains would be routed in the existing Caltrain rail corridor along the peninsula from San Jose to San Francisco.

Fundamentally everyone Continue reading “Shinkansen =”Train Envy””

The Worthwhile Cost of Customer Satisfaction – Building “Bridges to Nowhere”…

Can a project that is three years late after fourteen years in the making and costing $23.5 M instead of the $3 M originally budgeted be a success?

With numbers like this one would guess it was a “public works” project. Not quite a “bridge to nowhere” but more like a bridge that is somewhere… It is a small bridge that pales in comparison to the size and scope of the new $5.5 B East Span of the Bay Bridge (currently scheduled for completion in 2013). And unlike replacing the East Span, one could argue about the necessity of building this pedestrian and bicycle bridge in the first place.

Having visited the Sundial Bridge at Turtle Bay which crosses the Sacramento River in Redding, California last week and read some of the criticisms of the bridge, it made me stop and think “What are the true measures of success?”

Continue reading “The Worthwhile Cost of Customer Satisfaction – Building “Bridges to Nowhere”…”

SEMICON West: What a difference a year makes

Last week I was very busy visiting the combined SEMICON West and Intersolar North America trade shows in San Francisco. I had numerous meetings in addition to visiting the show floors and attending the excellent presentations. Based upon the lackluster show last year – I’ve heard some use “abysmal” to describe it – I almost hesitated to attend.

I’m happy to report that this year’s show was significantly better with a much more positive attitude and energy. SEMI’s preliminary attendance figure (for the combined show) is 29,461 which is up 32% from last year’s 17,048 verified attendance. This is significantly higher than both organizers expected. Intersolar had expected 1,600 visitors but had over twice as many. (The final numbers will be out in about two weeks in the “Post Show” report.)

Having attended for more than 15 years, Continue reading “SEMICON West: What a difference a year makes”

HOW and WHY things work!

The Art of the Teardown...

Miss Peach by Mell Lazarus (2/17/1974)

As a child I spent a lot of time taking things apart. My parents were relieved when a Miss Peach cartoon identified my behavior as explorative engineering rather than plain old fashioned destroying things. I was reminded of this again by the rash of recent blogs/articles by companies such as UBM Techinsights and Chipworks that estimate the cost of the iPhone 4 and similar devices-du-jour through teardowns. An excellent blog post last week by Steve Cheney recalled for me there’s a lot more to the story than simply documenting the bills of material (BOM) and estimating component costs.

Yes, it is interesting to know that the 16 GB iPhone 4 costs Apple approximately $188 in material and that you can buy one from AT&T (with a 2 year contract) for about the same price ($199). However, as a consumer, knowing this is simply “academic” since I can’t use this data to change the outcome: I either buy the phone or I don’t. Is there more to the story? Is there any real commercial value to a teardown?
Continue reading “HOW and WHY things work!”

IEEE Semiconductor Wafer Test Workshop – Awards & Wrap-up

The committee made the following awards for the presentations at the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW):

Most Inspirational went to two SV Probe authors:

Best Presentation, Tutorial in Nature went to Michael Huebner of FormFactor, “High Speed Control Bus for Advanced TRE”.

Best Data Presented – Denis Deegan of Analog Devices, “Contacting various metal compositions using ViProbe Vertical Technology”.

Best Presentation Overall – Matt Losey of Touchdown Technologies, “Low-Force MEMS Probe Solution for Full Wafer Single Touch Test”.

It is interesting to note that all but one of the papers cited above were in Session Eight – Area Array Probing of the workshop.

Also noted in the wrap-up remarks:

  • The final attendance count was 291.
  • Next year the conference will be June 12-15, 2011 at the Rancho Bernando Inn.

My impression from talking with many of my friends and colleagues at SWTW is that 2010 will be a very robust year especially in light of last year’s sharp decline. Here is hoping that the industry outperforms VLSIresearch’s forecast of 25.6% growth in 2010!

IEEE Semiconductor Wafer Test Workshop – Challenges of RF Probing – Session Nine (Wednesday)

Here are the highlights from Session Nine – Challenges of RF Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Ellis Huang, MPI Corporation, “Novel Vertical Probe Card Solution for Multi-DUTs and RF Device on 3 GHz Applications”:

This project was done with UMC using MPI’s VPC vertical probe technology to test Bluetooth modules at 2.45 GHz.

In order to provide a 50 ohm signal as close to the device under test (DUT) as possible, they added dummy ground pins to the probe head around critical signal pins.  Even though these signal pins already had adjacent ground pads that were probed on the device, these dummy pins (probes) were positioned closer to the signal pin thereby maintaining the 50 ohm impedance.  The dummy pins are connected to other grounds via the copper flex circuit on the space transformer.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Challenges of RF Probing – Session Nine (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)

Here are the highlights from Session Eight – Area Array Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:

Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found.  However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Seven (Tuesday)

Here are the highlights from Session Seven – Probe Potpourri of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:

For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test.  The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Seven (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Jay Thomas, Grund Technical Solutions, LLC., “Probe Cards with Modular Integrated Switching Matrices”:

For the last 30 years, most scribeline parametric testing has been approximately 85% Current-Voltage (I-V) testing and 15% Capacitance-Voltage (C-V) testing. For these types of tests a 10 MHz bandwidth switch matrix has been sufficient.

However, some of the larger fabs such as HP, IBM, and Intel have started performing pulsed Current-Voltage (PIV) and electrostatic discharge (ESD) testing. These customers started this type of testing about four years ago unknown to Agilent & Keithley (the two largest DC parametric tester suppliers). This PIV and ESD testing requires high frequency switch matrices with 1 GHz bandwidth. [For more about ESD testing please see Jay’s second presentation below in this session.]
Continue reading “IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:

For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk.  However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS).  Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)”

Missed Me?


For those who have been missing my blog updates – including the remaining IEEE Semiconductor Wafer Test Workshop posts – I’ve been on vacation with my family. While appreciating the natural beauty of six national parks, I’ve given considerable thought to what is next for me professionally…

3,800 miles later we’re back at home and I’ll be catching up on the blog shortly. Stay tuned!

IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)

Here are the highlights from Session Four – Standards and Methods of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW).

Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:

Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing.  A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications.  Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test.  These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)”

IEEE Semiconductor Wafer Test Workshop – Improving Cost of Ownership – Session Three (Monday)

Here are the highlights from Session Three – Improving Cost of Ownership of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Rey Rincon, Freescale & Jeff Greenberg, Rudolph Technologies, “Optimizing Test Cell Performance Using Probing Process Analysis and Predictive Scrub”:

Rey summarized efforts at Freescale to improve test cell performance with multi-tier cantilever probe cards by investigating prober performance, probe card performance and probe card analyzer correlation to the test cell.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Improving Cost of Ownership – Session Three (Monday)”

IEEE Semiconductor Wafer Test Workshop – High Temperature Probing – Session Two (Monday)

Here are the highlights from Session Two – High Temperature Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Keith Breinlinger, FormFactor, “Addressing the Operating Challenges of Full Wafer Contactors”:

Keith started by providing a real good analogy of the challenge of wafer probing in terms of contacting the edge of each sheet of papers in a sixteen high foot stack. He used the new full wafer probe cards SmartMatrix (DRAM) and the TouchMatrix (NAND FLASH) as the basis of his presentation.
Continue reading “IEEE Semiconductor Wafer Test Workshop – High Temperature Probing – Session Two (Monday)”

IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)

Here are the highlights from Session One – New Contact Technologies of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Jay Kim, Western Specialty Technologies, LLC, “New Probe Card Architecture – Ceramic without MLC”:

He showed how Fine Instrument Co., Ltd.  (Korea) built a new probe card architecture which eliminates using multi-layer ceramics (MLCs) to avoid the cost and lead times issues.
Continue reading “IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)”

IEEE Semiconductor Wafer Test Workshop – Opening Session (Sunday)

The 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) started this evening. Rumor has it that attendance is over 240 this year which is a vast improvement over last year’s 160 or so attendees. At the peak the conference had almost hit 600. Things started off well with a reception where I had the chance to catch up with many industry friends and colleagues.

After dinner, Jerry Broz the General Chair kicked things off with the “Probe Year in Review”. In summary:
Continue reading “IEEE Semiconductor Wafer Test Workshop – Opening Session (Sunday)”

FIFO, LIFO or Fido? What to do first.

Which way to go?
When overwhelmed by production, “Test” or “Quality Control” must learn to think globally rather than just functionally. Historically most companies always test first-in, first-out (FIFO) but should be prepared to abandon that practice when facing a backlog. An analogy is a navigator letting the pilot know they are off course right now versus discussing history from three hundred miles ago and working their way up to the present.

Recently a colleague was concerned that his company’s test capacity was insufficient to test all their output in a timely manner. (They manufacture integrated circuits with several hundred devices on each wafer produced.) In fact, the backlog of parts to be tested was approaching six weeks since additional test cells were not ready. After he explained the multitude of reasons why the additional test cells were not ready and that production could not be slowed to match the available test capacity, I asked how they were handling the backlog. He appeared perplexed by my question and wanted to know why it wasn’t obvious that they would simply test them in FIFO order as they had always done.
Continue reading “FIFO, LIFO or Fido? What to do first.”

IEEE Consumer Electronics Society – Conductive Inkjet Technology

Last night I attended the IEEE Santa Clara Valley Consumer Electronics Society monthly meeting. The main presentation was by Joel Yocom, Business Development Manager for Conductive Inkjet Technology Ltd.

His presentation will be posted here later.

Joel presented an overview of inkjet technology and how they are applying it to printing circuits. They have developed a process that allows them to inkjet a catalytic ink which after UV curing allows the electroless (e-less) plating of copper. Given the choice of inkjet systems from scanning formats where the print head moves to fixed heads where the material moves past the head they have a wide range of potential substrate sizes and formats to choose depending on the end application. Continue reading “IEEE Consumer Electronics Society – Conductive Inkjet Technology”

IEEE Nanotechnology Symposium – Session 7 – Nano-Enabled Energy II


Here are the highlights from Session 7 – Nano-Enabled Energy II from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Dr. David Predergast, Lawrence Berkeley National Laboratory (LBNL) Molecular Foundry, “Nature of Nano-Scale Interfaces and Mechanisms for Solar Energy Conversion.”

IEEE Nanotechnology Symposium – Session 6 – Nano-Electronics


Here are the highlights from Session 6 – Nano-Electronics from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Vijendra Sahi, VP Corporate Development and GM of the QD Soleil division, Nanosys, Inc.

“From Concept to Creation: The Journey from R&D to Everyday Products.”

IEEE Nanotechnology Symposium – Day Two – Plenary


Here are the highlights from the Plenary session on day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Dr. Burton Lee, Stanford University, “State of European Nanotech.”

IEEE Nanotechnology Symposium – Session 5 – Nano-Processes


Here are the highlights from Session 5 – Nano-Processes from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Dr. Hans Stork, VP and CTO Applied Materials, “Nanotechnology in Semiconductor Industry.

IEEE Nanotechnology Symposium – Session 4 – Nano Materials

Here are the highlights from Session 4 – Nano Materials from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Eric Granstrom, General Manager and V.P. of R&D, Cima NanoTech – “Self Aligning Nano Technology for Electronics.”

  • First product Self Aligning Nano Technology for Transparent Electronics (SANTE) is transparent conductive film produced by self aligning silver nanoparticles.
  • For the same transparency, it has 1/10 the resistance of Indium Tin Oxide (ITO).  Also doesn’t yellow shift the color.
  • Based upon current consumption, it is projected that there is only a 7 year supply of ITO.  China controls 80% of this supply.
  • Largest initial market is displays which have one or more (LCDs have two) conductive films.
  • Continue reading “IEEE Nanotechnology Symposium – Session 4 – Nano Materials”

IEEE Nanotechnology Symposium – Day One (Sessions 1 – 3)

Here are today’s highlights from the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Dr. Michael Liehr, VP Strategy CNSE Albany, “State of US Nanotech.

  • College of Nanoscale Science and Engineering (CSNE).  Not organized around traditional degrees (ME, EE, Chem-E, etc.) but around nanoscience, nanoengineering, nanobioscience, & nanofinance.
  • Due to R&D increasing as a percentage of revenue, very few companies will be able to continue making the investments in process development on their own.  Therefore, over time there will be a migration to 2 or 3 technology clusters (or “camps”) worldwide.
  • Continue reading “IEEE Nanotechnology Symposium – Day One (Sessions 1 – 3)”

Pass or Fail? The Limits of Integrated Circuit Testing

Balancing test coverage versus test cost. What does a test failure mean? Value of yield increase

… and how it impacts your bottom line!

A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.

A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.

Continue reading “Pass or Fail? The Limits of Integrated Circuit Testing”

Richard Elkus – Winner Take All

US is losing its competitiveness due to financial issues and off-shoring of production.

Tonight I attended an excellent presentation by Richard Elkus, Jr. at the IEEE Components, Packaging, and Manufacturing Technology Society (CPMT) Santa Clara Valley Chapter monthly meeting. He spoke about how the United States is losing its global competitiveness due to our financial issues and our inability to manufacture technology domestically.

Early in his career at Ampex he did the product planning for and led the team that introduced the VCR. In 1970, they partnered with Toshiba to manufacturer the units. He then illustrated with multiple examples,  how we lost our ability to innovate and to remain competitive when we “off shored” the production of a given technology. This is also the subject of his book Winner Take All: How Competitiveness Shapes the Fate of Nations.

IEEE 125th Anniversary Celebration

Computer History Museum by Dzou @ wikipedia.org
You can always learn something by hearing top notch presenters speak both in terms of content and style. And even after traveling the world, you may find hidden gems in your own backyard…

This evening I attended a local celebration for IEEE‘s 125th Anniversary. This was structured as a reception (code word: “networking”) followed by several keynote speeches.

First up on the program was a presentation to SRI (formerly known as the Stanford Research Institute) to recognize the 40th anniversary of the first transmission on the the ARPANET (the predecessor of the internet). At that time there were just four nodes: SRI, UCLA, UC Santa Barbara and University of Utah. A large number of the original engineers were on hand to have their achievement recognized.
Continue reading “IEEE 125th Anniversary Celebration”