CMOS Imagers – High Technology Business Development

Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span Continue reading “Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Continue reading “IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)”