High Volume Manufacturing (HVM) – High Technology Business Development

SEMI ISS: Sense of Scale

Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013

Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.

The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers ~~needing~~ wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.

The whiplash comes from Continue reading “SEMI ISS: Sense of Scale”

MEMS Testing and Reliability 2012 – Session 4

Can reliability and production testing keep pace with the explosive growth in microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 4

Mervi Paulasto-Kröckel (Professor, Aalto University) in “On the Reliability Characterization of MEMS Devices” examined the current methods for reliability assessment in MEMS devices and identified necessary improvements. Currently, the reliability of MEMS devices are evaluated in the functioning state. A sensor is tested by applying a known stimulus and comparing the sensor output while varying the test conditions such as temperature, humidity, etc. MEMS actuators are similarly tested by providing a known input and measuring the output of the actuator over the range of test conditions. Significant deviation between the expected and measured result indicates a failure. Simple functional test is appropriate for manufacturing quality testing however it is inadequate for measuring and improving device reliability.

Professor Paulasto-Kröckel compared these processes commonly used to estimate MEMS reliability to those used in the microelectronics industry. She identified major methodology changes required Continue reading “MEMS Testing and Reliability 2012 – Session 4”

MEMS Testing and Reliability 2012 – Session 3

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren’t really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of Continue reading “MEMS Testing and Reliability 2012 – Session 3”

MEMS Testing and Reliability 2012 – Session 2

Session 2

Mårten Vrånes (Director of Consulting Services, MEMS Journal) in “A Test-centric Approach to MEMS ASIC Development” discussed alternatives to the traditional co-design of the MEMS element and application specific integrated circuit (ASIC). As many MEMS devices require an ASIC to control and/or sense the MEMS element the most logical approach is to design both parts in parallel. However the scope of such a development effort is often beyond the resources – both in terms of talent and funding – for many companies especially startups.

Mr. Vrånes started with the challenges and pitfalls of ASIC development for MEMS devices. There are challenges regardless of Continue reading “MEMS Testing and Reliability 2012 – Session 2”

MEMS Testing and Reliability 2012 – Session 1

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960’s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960’s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include Continue reading “MEMS Testing and Reliability 2012 – Session 1”

IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

Thinking Big: $1 Trillion MEMS Market – Part 2

Part 1 described Janusz Bryzek‘s ambitious goal of a $1 trillion market for microelectromechanical systems (MEMS) that was the focus of the MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium. In addition, sensor swarms, road mapping and market numbers were covered. Challenges, example applications, and key takeaways are discussed here along with a final score card on the $1 T market.

Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 2”

Thinking Big: $1 Trillion MEMS Market – Part 1

Usual business advice includes thinking big to win big. Some organizations create Big Hairy Audacious Goals. Others like to find new markets that are underserved and grow to be number one. The semiconductor industry has Moore’s Law – the premise that the minimum cost point is achieved by doubling the number of transistors per chip every two years – driving it forward for almost fifty years.

Janusz Bryzek set a dramatic and ambitious goal of $1 trillion sales for the microelectromechanical systems (MEMS) market in 2022. Even though the MEMS market is expected to have “only” $12 billion in revenue in 2012, he isn’t being called a fool. Having cofounded eight seminal Silicon Valley MEMS companies and currently the Vice President of MEMS Development at Fairchild Semiconductor (which recently acquired his last company), Janusz is taken quite seriously.

Yes, at last week’s MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium there were some who Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 1”

Green on the Industrial Scale

MLD George-Yoon-Dameron ACS — Molecular Layer Deposition of Polymers – George, Yoon & Dameron [4]

Many exotic materials or materials with special properties are processed using extreme temperature and pressure often with toxic starting materials. In semiconductors, molecular beam epitaxy (MBE) to build single crystal structures and sputtering are common methods of physical deposition to deposit thin films. Both are done using a very high vacuum. MBE heats the atomic materials until they sublimate and land on the desired surface. Sputtering uses a gas plasma to knock a few atoms of material off a “target” and onto the desired surface. There are also different chemical deposition processes including electroplating which uses metal salts dissolved in a solution bath, chemical vapor deposition (CVD) which uses high vacuum, and atomic layer deposition (ALD) which is similar to CVD but uses two half-reactions of gas phase precursors.

Limitations imposed by extreme temperature, extreme pressure, and toxic materials combined with a typically slow deposition rate make it is difficult to economically run these processes on an industrial scale for high volume manufacturing. But what if there was a process that Continue reading “Green on the Industrial Scale”

IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”

Probe Card Cost Drivers from Architecture to Zero Defects

Click to download presentation — Click image to download presentation

As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.

Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.

Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.

There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.

I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.

Beware the Cost of Complexity

Early in my career in Hewlett-Packard manufacturing, we did a study that showed that the greater the configuration options we put on a single product the higher the cost to produce every other product in the same factory. Known as “Cost of Complexity” this has been found in many different industries with examples from software coding, to network support to food production. Not to mention in our own products, companies, and everyday lives.

Continue reading “Beware the Cost of Complexity”

IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Jay Thomas, Grund Technical Solutions, LLC., “Probe Cards with Modular Integrated Switching Matrices”:

For the last 30 years, most scribeline parametric testing has been approximately 85% Current-Voltage (I-V) testing and 15% Capacitance-Voltage (C-V) testing. For these types of tests a 10 MHz bandwidth switch matrix has been sufficient.

However, some of the larger fabs such as HP, IBM, and Intel have started performing pulsed Current-Voltage (PIV) and electrostatic discharge (ESD) testing. These customers started this type of testing about four years ago unknown to Agilent & Keithley (the two largest DC parametric tester suppliers). This PIV and ESD testing requires high frequency switch matrices with 1 GHz bandwidth. [For more about ESD testing please see Jay’s second presentation below in this session.]
Continue reading “IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:

For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk. However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS). Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Improving Cost of Ownership – Session Three (Monday)

Here are the highlights from Session Three – Improving Cost of Ownership of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Rey Rincon, Freescale & Jeff Greenberg, Rudolph Technologies, “Optimizing Test Cell Performance Using Probing Process Analysis and Predictive Scrub”:

Rey summarized efforts at Freescale to improve test cell performance with multi-tier cantilever probe cards by investigating prober performance, probe card performance and probe card analyzer correlation to the test cell.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Improving Cost of Ownership – Session Three (Monday)”

IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)

Here are the highlights from Session One – New Contact Technologies of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Jay Kim, Western Specialty Technologies, LLC, “New Probe Card Architecture – Ceramic without MLC”:

He showed how Fine Instrument Co., Ltd. (Korea) built a new probe card architecture which eliminates using multi-layer ceramics (MLCs) to avoid the cost and lead times issues.
Continue reading “IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)”

FIFO, LIFO or Fido? What to do first.

When overwhelmed by production, “Test” or “Quality Control” must learn to think globally rather than just functionally. Historically most companies always test first-in, first-out (FIFO) but should be prepared to abandon that practice when facing a backlog. An analogy is a navigator letting the pilot know they are off course right now versus discussing history from three hundred miles ago and working their way up to the present.

Recently a colleague was concerned that his company’s test capacity was insufficient to test all their output in a timely manner. (They manufacture integrated circuits with several hundred devices on each wafer produced.) In fact, the backlog of parts to be tested was approaching six weeks since additional test cells were not ready. After he explained the multitude of reasons why the additional test cells were not ready and that production could not be slowed to match the available test capacity, I asked how they were handling the backlog. He appeared perplexed by my question and wanted to know why it wasn’t obvious that they would simply test them in FIFO order as they had always done.
Continue reading “FIFO, LIFO or Fido? What to do first.”

IEEE Consumer Electronics Society – Conductive Inkjet Technology

Last night I attended the IEEE Santa Clara Valley Consumer Electronics Society monthly meeting. The main presentation was by Joel Yocom, Business Development Manager for Conductive Inkjet Technology Ltd.

His presentation will be posted here later.

Joel presented an overview of inkjet technology and how they are applying it to printing circuits. They have developed a process that allows them to inkjet a catalytic ink which after UV curing allows the electroless (e-less) plating of copper. Given the choice of inkjet systems from scanning formats where the print head moves to fixed heads where the material moves past the head they have a wide range of potential substrate sizes and formats to choose depending on the end application. Continue reading “IEEE Consumer Electronics Society – Conductive Inkjet Technology”

IEEE Nanotechnology Symposium – Session 5 – Nano-Processes

Here are the highlights from Session 5 – Nano-Processes from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6^th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Dr. Hans Stork, VP and CTO Applied Materials, “Nanotechnology in Semiconductor Industry.”

Important to look at market trends. However for an equipment manufacturer, need to look at wafer volumes (area) more than unit volumes due to die shrinks.

Continue reading “IEEE Nanotechnology Symposium – Session 5 – Nano-Processes”

Pass or Fail? The Limits of Integrated Circuit Testing

Balancing test coverage versus test cost. What does a test failure mean? Value of yield increase

… and how it impacts your bottom line!

A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.

A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.

Continue reading “Pass or Fail? The Limits of Integrated Circuit Testing”