Semiconductor Wafer Test Workshop 2015 Presentation – Are You Really Going To Package That?

Are You Really Going To Package That? - Ira Feldman and Debbora Ahlgren - SW Test 2015
Click image to download presentation

I had the pleasure of presenting “Are You Really Going To Package That?” at the 25th annual Semiconductor Wafer Test Workshop (SW Test / SWTW) on Tuesday June 9, 2015. Debbora Ahlgren and I took this opportunity to step back and look at how old paradigms in test-cell integration may lead to suboptimal solutions.

In an effort to reduce the cost-of-test (COT), a number of customers are increasing the parallelism of logic wafer probe cards. However, due to the complexity such as pitch and number of probes, the pricing for these cards is reaching astronomical levels. We do not believe this trend is sustainable, let alone logical. The presentation suggested examples of alternative solutions. It is clear that critical solutions need to be optimized at the test cell, factory, and supply chain level not just at the consumable (probe card) level.

IEEE Semiconductor Wafer Test Workshop 2014 Presentation

International Technology Roadmap for Semiconductors (ITRS) - Ira Feldman - IEEE SWTW2014
Click image to download presentation

At the 24th annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) on Wednesday June 11, 2014,
I had the pleasure of presenting “International Technology Roadmap for Semiconductors”. This presentation was co-authored with Dave Armstrong (Advantest) and Marc Loranger (FormFactor).

For the last fifteen years the International Technology Roadmap for Semiconductors (ITRS) has been looking fifteen years into the future. Based upon technology requirements and other inputs, ranging from the gate size of transistors to advanced packaging technology, the Test and Test Equipment Technical Working Group (Test TWG) has worked to develop the requirements for test technology and equipment.

The Test TWG is over seventy volunteers with deep technical expertise in test from around the world and from every sized company – Fortune 100 to individual consultants – and every type of company – semiconductor independent device manufacturer (IDM), fabless semiconductor, foundry, outsourced assembly and test (OSAT), automated test equipment (ATE) suppliers, prober, probe card, socket, handler, and more. Through Continue reading “IEEE Semiconductor Wafer Test Workshop 2014 Presentation”

BiTS Workshop – The Next 15 Years

Thanks to the BiTS Committee for the hard work to make this a great event!
Thanks to the BiTS Committee for the hard work to make this a great event!

Wow! The Burn-in and Test Strategy (BiTS) Workshop just turned 15! The world of semiconductors has certainly changed over the years. And the BiTS Workshop has kept up with what is “Now & Next” in the burn-in and test of packaged integrated circuits (ICs). These achievements were celebrated in style by the more than three hundred participants at the recently held 2014 BiTS Workshop in Mesa, Arizona.

“When the BiTS Workshop started in 2000, there were no Continue reading “BiTS Workshop – The Next 15 Years”

Chip Scale Review: The Three Most Important Words for 3D ICs?

Source: Bryan Black (AMD)
Source: Bryan Black (AMD)

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Continue reading “Chip Scale Review: The Three Most Important Words for 3D ICs?”

Coupling & Crosstalk: Name Calling

good bad dice canstockphoto9654181 250x320Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2013 edition on pages 13-14.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Name Calling

What’s in a name? A lot! A name itself might not mean much but it can trigger expectations and stereotypes. In the United States we have red states and blue states depending on which political party has the majority vote. Similarly, when someone labels themselves on the basis of their political party affiliation (Republican, Democrat, Libertarian, Independent, etc.) others Continue reading “Coupling & Crosstalk: Name Calling”

Riding Off Into the Sunset – BiTS 2013

Sunset over Phoenix, Arizona during BiTS Workshop
Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Continue reading “Riding Off Into the Sunset – BiTS 2013”

SEMI ISS: Sense of Scale

Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013
Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013

Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.

The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.

The whiplash comes from  Continue reading “SEMI ISS: Sense of Scale”