Tag: Photolithography

SEMI ISS 2014 – Scaling Innovation

Courtesy of Ivo Bolsens (Xilinx), SEMI ISS 2014
Courtesy of Ivo Bolsens (Xilinx), SEMI ISS 2014

Don’t pop the champagne just yet! Although plenty of good news was shared at the 2014 SEMI Industry Strategy Symposium (ISS) there was the sobering outlook of possible limited long-term growth due to technology issues as well as economic projections. Noticeable was the lack of news and updates on key industry developments.

This is the yearly “data rich” or “data overload” (take your pick) conference of semiconductor supply chain executives. The majority of the attendees and presenters are from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. Keeping the pressure on for advanced technology were the “end customer” attendees and presenters – semi-conductor manufacturers.

The official theme was “Pervasive Computing – An Enabler for Future Growth” and the presentations made it clear  Continue reading “SEMI ISS 2014 – Scaling Innovation”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

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Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”