Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2016 edition on pages 8-9.
Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
Quality, Meet Safety & Security!
What can be simpler to specify or install than a light bulb controlled by a wall switch? Over-engineered versions, especially when developed without engineers, can really cause you to lose sleep. However, the real nightmare is the danger of Continue reading “Coupling & Crosstalk: Quality, Meet Safety & Security!”
Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2012 edition on page 12-13.
Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
Quality for the Long Haul?
Does a manufacturer’s responsibility and interest in quality end when the warranty expires?
When is death premature? People have life expectations based upon family and societal statistics as well as their health. Mechanical devices, especially those with moving parts, have estimated lives and known wear out mechanisms. Cars currently have an average age of 11 to 13 years of useful life which allows consumers to set reasonable expectations of service life. What about electronics? What is a reasonable expectation of service life?
I had a few devices at home fail recently which makes me wonder about Continue reading “Coupling & Crosstalk: Quality for the Long Haul?”
Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:
Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.
These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”
When overwhelmed by production, “Test” or “Quality Control” must learn to think globally rather than just functionally. Historically most companies always test first-in, first-out (FIFO) but should be prepared to abandon that practice when facing a backlog. An analogy is a navigator letting the pilot know they are off course right now versus discussing history from three hundred miles ago and working their way up to the present.
Recently a colleague was concerned that his company’s test capacity was insufficient to test all their output in a timely manner. (They manufacture integrated circuits with several hundred devices on each wafer produced.) In fact, the backlog of parts to be tested was approaching six weeks since additional test cells were not ready. After he explained the multitude of reasons why the additional test cells were not ready and that production could not be slowed to match the available test capacity, I asked how they were handling the backlog. He appeared perplexed by my question and wanted to know why it wasn’t obvious that they would simply test them in FIFO order as they had always done.
Continue reading “FIFO, LIFO or Fido? What to do first.”
Balancing test coverage versus test cost. What does a test failure mean? Value of yield increase
… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.
Continue reading “Pass or Fail? The Limits of Integrated Circuit Testing”