Interconnectology – High Technology Business Development

BiTS Workshop – The Next 15 Years

Thanks to the BiTS Committee for the hard work to make this a great event!

Wow! The Burn-in and Test Strategy (BiTS) Workshop just turned 15! The world of semiconductors has certainly changed over the years. And the BiTS Workshop has kept up with what is “Now & Next” in the burn-in and test of packaged integrated circuits (ICs). These achievements were celebrated in style by the more than three hundred participants at the recently held 2014 BiTS Workshop in Mesa, Arizona.

“When the BiTS Workshop started in 2000, there were no Continue reading “BiTS Workshop – The Next 15 Years”

Chip Scale Review: The Three Most Important Words for 3D ICs?

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Continue reading “Chip Scale Review: The Three Most Important Words for 3D ICs?”

Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Market adoption is increasing rapidly for wafer level packaging (WLP) as it is applied to a greater range of applications. The shift of “Post-PC” from desktop to mobile devices has driven the development of WLP into the mainstream by providing extremely space efficient and low cost packaging. There has and will continue to be many technical and business challenges in packaging devices on wafer (or other substrate) en masse instead of on an individual basis.

Similar to wafer level packaging technology itself, the 2013 International Wafer-Level Packaging Conference (IWLPC) Continue reading “Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!”

IEEE Semiconductor Wafer Test Workshop 2013

Ideal 3D Stacked Die Test - Ira Feldman - IEEE SWTW2013 — Click image to download presentation

I had the pleasure of presenting “Ideal 3D Stacked Die Test” in Session Two “Industry Trends and Advanced Packaging Challenges” of the 23rd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) on Monday June 10, 2013.

Integrated circuits using 2.5D advanced packaging are shipping. 3D packaging with thru-silicon vias (TSV) has been demonstrated. “5.5D” packages may not be far behind. Probe card suppliers have made progress building interconnect technology for the micro-bump arrays. Standards committees have started defining IC interface standards and test access protocols.

But what does the Test Engineer and Management really want? What can they afford? What are the most likely scenarios? Factors that determine which test technology can support the desired test flow are examined. In particular, probe card technology for probing TSV bumps and potential usage models are reviewed.

Riding Off Into the Sunset – BiTS 2013

Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Continue reading “Riding Off Into the Sunset – BiTS 2013”