Chip Scale Review: The Three Most Important Words for 3D ICs?

Source: Bryan Black (AMD)

Source: Bryan Black (AMD)

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from should we build, to what we need to build, to how do we build 2.5/3D. The underlying current this year is what is needed to build 2.5/3D profitably. Do not forget, repeatable and high yield processes are essential to profitability.

Doug Yu (Taiwan Semiconductor Manufacturing Company) in his keynote “Déjà Vu – Wafer Level System Integration Technology,” described the challenges of developing 2.5/3D technologies that they call “WLSI”. These challenges are similar to the ones TSMC has faced and continues to face in keeping very-large-scale integration (VLSI) technology on pace with Moore’s Law. The main distinction is that VLSI is primarily concerned with on-chip interconnect while WLSI is focused on off-chip interconnect. As Moore’s Law slows down or ends for transistor scaling due to technological and/or cost issues, they believe WLSI will provide the required path forward for the industry.

3D technology creates new challenges, especially in the area of test complexity. In order to be successful one needs to use the challenges to do things differently. This was the message of Robert Patti (Tezzaron Semiconductor and event co-chair) when describing their advanced high-density high-performance memory solutions. For example, Tezzaron does not worry about having known good die (KGD) by testing and repairing wafers before stacking. Instead, they have very high levels of built in self-test (BIST), redundancy, and repair capabilities on the presumption that there will be many defects either in the memory cell levels or wafer-to-wafer interconnect. Counter-intuitively as they stack more die, the final yield goes up as they have more capacity for repair.

Patti said that due to the complexity of the assembly and test process, 2.5/3D devices are not going to be less expensive than existing devices. However, they may make sense at the system level enabling performance and capability that cannot be built any other way or at a lower system cost.

Philip Garrou (Microelectronic Consultants of NC and event co-chair) reviewed the current status of products which previously announced or suggested they would be using through silicon vias (TSV) and 2.5/3D packaging. Unfortunately, of the eight products listed five changed plans, one does not appear likely, and the remaining two are due in 2014/15 and 2016. On the good news side, he did show a Sony complementary metal-oxide-semiconductor (CMOS) image sensor that is using TSVs to stack an imager array with logic. Thus “true 3D” versus simply using TSVs to interconnect the sensor to the package. He also provided overviews on 3D memory, interposers, and bonding. Garrou closed with a quote from Mark Bohr, Chief Technology Officer of Intel, highlighting the real issue of TSV and 3D technology is cost and that not all markets will bear the higher cost.

A number of the presenters focused on the benefits of heterogeneous integration mixing die in 2.5/3D packages from different technology nodes (such as 60 nm and 28 nm) and even different fabrication processes (different “flavor” of CMOS or different materials altogether such as CMOS and gallium arsenide for example).

The economic advantage of mixing technology nodes was mentioned by many of the speakers including Garrou, Javier DeLaCruz (eSilicion), and Brandon Wang (Cadence Design Systems). Wang provided specific cost estimates of placing a design on the latest and greatest process node. If the design cost alone is $50-90 M for the 32/28 nm node versus $120-500 M for 22/20 nm node, why move the entire IC design from 32 to 22 nm? If portions of the design are available and proven on 32 nm (or even older process node), why not just move the portion of the design that requires the increased performance to the 22 nm node and then stack the two or more dies in a 2.5/3D package? This would reduce the size of the 22 nm die to the absolute minimum thereby increasing its yield and decreasing cost. And it would allow the existing design (on 32 nm) to be reused without the cost and expense of fully characterizing it again, required if moved to 22 nm. By simplifying the new and unproven portion of the design, 2.5/3D should also accelerate time to market for new designs.

Many of the presenters also discussed integrating different fabrication processes to achieve needed performance. Today’s high performance microprocessors and graphical processor units (GPU) contain a wide variety of circuitry that requires using a single fabrication process since the circuitry is on one IC. This fabrication process may be sub-optimal for many parts of the design since it needs to work for all the circuitry. Adding more circuitry and “stretching” the process may in fact be lowering the performance of the entire design according to Bryan Black (AMD). Instead of adding more and more functions into future processor designs, Black said they would split a processor into many different dies each built with the optimum fabrication process for that particular circuitry. He stated AMD would be “very aggressive” in their designs using 2.5D, 3D, and multi-chip module (MCM) technology all at the same time possibly with as many eighty (yes 80!) different dies on the substrate.

Beyond CMOS based fabrication processes, there was also a focus on the integration of photonic elements. The preconference symposium “Silicon Photonics: Coming of Age” had five informative presentations on silicon photonics and how they are being integrated into 2.5/3D packaging. Even more so than IC designs, the photonic designs are extremely sensitive to the process technology and process node. Once built and characterized it is extremely difficult and expensive to move to another node even of the same process. Not only does 2.5/3D integration allow the decoupling of the photonics from the logic, it also allows reuse of proven design and elements.

Surya Bhattacharya (Institute for Microelectronics) explained their development programs, including silicon photonics, for the platform they are developing for data centers and high performance computing (HPC). In their imaging work, John Lannon (RTI International) presented their work bonding to silicon logic dies to non-silicon imagers such as those built with indium phosphide (InP), mercury cadmium telluride (HgCdTe), and other materials. Similarly Miguel Urteaga (Teledyne Scientific Company) explained integrating to advanced group III-V materials.

In his keynote, Kaivan Karimi (Freescale) further emphasized the essential need for 3D packaging to support heterogeneous integration for the Internet of Things (IoT). Edge nodes (the “things” that sense and/or interact with the physical world) require functionality such as wireless communication, sensing, analog circuitry, memory, and ultra low power computation. These disparate elements need to be built using optimized fabrication processes instead of one generic process for the best performance and lowest cost.  And there are some elements that require packaging integration since they cannot be built with a standard CMOS process. For example, a micro-electromechanical systems (MEMS) sensor, which has to be built with its own, dedicated process.

There were many other excellent papers highlighting progress towards 2.5/3D integration in terms of materials, processes, and equipment. As Jan Vardaman (TechSearch International) highlighted in her “report card”, there are many areas that have improved but there are several incompletes and low grades that need to be addressed. Yes, the industry has proven the technology can work – now it needs to be determined how to do it at scale and profitably. Otherwise, 2.5/3D will be limited to only extreme applications with unlimited budgets or extremely low volumes.

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