Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers

October 31, 2011
Lessons for MEMS Test Engineers

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The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.

My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.

I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.

With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.

IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

October 17, 2011


Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Read the rest of this entry »

IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

June 29, 2011

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Read the rest of this entry »

How to re-FORM or refill a fab

October 18, 2010

Fill 'er Up To Make Money

I usually try to ignore items that are unattributed, however a recent blog posting in the ElectroIQ blog “How To Fix FORM” caught my attention. It is true that FormFactor’s current difficulties are being discussed widely. However, the simplistic analysis and suggestions of this unknown “industry insider” need a reality check. The writer gets some of the overall problems right but may be missing the boat on the solutions.

Here are the supposed anonymous industry insider’s suggested fixes:

Read the rest of this entry »

FIFO, LIFO or Fido? What to do first.

June 2, 2010

Which way to go?
When overwhelmed by production, “Test” or “Quality Control” must learn to think globally rather than just functionally. Historically most companies always test first-in, first-out (FIFO) but should be prepared to abandon that practice when facing a backlog. An analogy is a navigator letting the pilot know they are off course right now versus discussing history from three hundred miles ago and working their way up to the present.

Recently a colleague was concerned that his company’s test capacity was insufficient to test all their output in a timely manner. (They manufacture integrated circuits with several hundred devices on each wafer produced.) In fact, the backlog of parts to be tested was approaching six weeks since additional test cells were not ready. After he explained the multitude of reasons why the additional test cells were not ready and that production could not be slowed to match the available test capacity, I asked how they were handling the backlog. He appeared perplexed by my question and wanted to know why it wasn’t obvious that they would simply test them in FIFO order as they had always done.
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