Chip Scale Review: The Three Most Important Words for 3D ICs?

December 19, 2013
Source: Bryan Black (AMD)

Source: Bryan Black (AMD)

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Read the rest of this entry »


Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!

December 10, 2013

IWLPC_logo

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Market adoption is increasing rapidly for wafer level packaging (WLP) as it is applied to a greater range of applications. The shift of “Post-PC” from desktop to mobile devices has driven the development of WLP into the mainstream by providing extremely space efficient and low cost packaging. There has and will continue to be many technical and business challenges in packaging devices on wafer (or other substrate) en masse instead of on an individual basis.

Similar to wafer level packaging technology itself, the 2013 International Wafer-Level Packaging Conference (IWLPC) Read the rest of this entry »


Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

December 19, 2012
Lego Blocks (flickr: antpaniagua)

Lego Blocks (flickr: antpaniagua)

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span Read the rest of this entry »