Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

Lego Blocks (flickr: antpaniagua)

Lego Blocks (flickr: antpaniagua)

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span the fundamental technology and the entire supply chain from design, equipment, materials, test, and suppliers. Liam Madden (Xilinx) described how they had to “cobble together” design tools to solve the cross-domain (thermal, electrical, and mechanical) cross-die problems of their ground breaking Virtex-7 2.5D designs. Even though Vinod Kariat (Cadance Design Systems) characterized Xilinx’s initial challenges as “stretching” the existing design tools, he and Steve Smith (Synopsys) reviewed the great progress made in their respective tools to support 3D design. Smith also showed the future of 3D packaging beyond semiconductors to include microelectromechanical systems (MEMS) to support new and innovative products. (Who says you don’t need an inflatable scarf helmet?)

When developing new technology “tribal knowledge” needs to be converted into design rules. These rules are then updated based upon simulation, test vehicle results, and product learning says Riko Radojcic (Qualcomm). Without such a process, there is no structured learning to guide product development. There is also a need for additional information, beyond existing process design kits (PDKs), to describe a die design to permit cross-domain and cross-die designs and analysis. Lisa McIlrath (R3Logic) described their work in supporting such 3D designs including how to manage this “super PDK” data. Having completed 3D designs such as WIOMING with very high memory bandwidth, Denis Dutoit (CEA-Leti) described their design “libraries” and “toolkit” of processes they developed.

Thorsten Matthias (EV Group) and Wilfried Bair (SUSS MicroTec) each presented the challenges and status of their process equipment with an emphasis on bond and de-bond of wafers to temporary process carriers. Numerous speakers, including John Lannon (RTI International) who shared leanings from an image sensor integration program, expressed concerns that wafer bond/de-bond still requires signficant progress in terms of robustness and cost reduction.

Glass and laminate interposers where discussed as cost reductions options by Arifur Rahman (Altera Corporation) and Paul Silvestri (Amkor Technology). However, Phil Garrou (Microelectronic Consultants of NC) said to not expect glass interposers from existing players, especially outsourced assembly and test (OSAT) providers, due to the high capital costs (~$6.5B) of a glass panel facility.

In terms of an “open” supply chain for silicon interposers, David McCann (GLOBALFOUNDRIES) said they would be ready when the customers are. Paul Silvestri (Amkor Technology) similarly reviewed their progress and readiness to process through silicon vias (TSV), thin wafers, and integrate die. Interposers and TSV processing are ready for customers said Patrick Leduc (CEA-Leti) and Juergen Wolf (Fraunhofer IZM-ASSID). For assembly, Chris Sanders (Ziptronix) reviewed the status of their bonding processes available for licensing. Sesh Ramaswami (Applied Materials) discussed process and equipment developments to support customer technology and reduce costs.

Test methodologies where covered by Erik Jan Marinissen (IMEC) in terms of test access and control via scan interfaces (existing standards and those under development) in addition to physical wafer probe. Bassilios Petrakis (Cadence Design Systems) discussed how their tools support logic core “wrappers” and generation of scan vectors that result in negligible increases in die area and test times. Results from TSV micro-bump wafer probing experiments were shared by Daniel Rishavy (Tokyo Electron America). Dutoit also touched on the portioning of the test strategy necessary for 3D designs.

Two end application trends were visible to solve memory and bandwidth challenges. Robert Patti (Tezzaron Semiconductor) and Thomas Pawlowski (Micron) each discussed the required disassociation of memory device interfaces from the underlying memory technology. Madden and Carl Engblom (Ericsson) each started the conference with keynotes discussing the need for high speed data in the 100 Gb/s to 400 Gb/s range which can only be supported with optical interconnects. Wolf, Rahaman, Surya Bhattacharya (A*Star Institute of Microelectronics), and John Cunningham (Oracle Corporation) also reviewed the need for and solutions using optical interconnects.

Cost is an ever-present challenge touched on by many. Madden described “Stackonomics” using advanced packaging to combine logic, memory, and/or analog dies since process optimization makes it impractical to build a single piece of silicon combining two or more of these functions. Marinissen (IMEC) also reviewed a cost model to evaluate options for testing 3D packaging. Standards to reduce development and high volume production costs were discussed by Minsuk Su (Sematech/SK Hynix) and Radojcic.

Jan Vardaman (TechSearch International) provided a market overview including the “real work” to make 2.5D happen and the cost tradeoffs being made versus existing technology. According to Lionel Cadix (Yole Développement), the hybrid memory cube (HMC) will be commercialized in 2013 and 3D packaging will grow at a rate 10x that of semiconductors to $40B in 2017. Cadix’s cost model of the Xilinx 2.5D technology provoked lively discussions. Garrou also provided sanity based upon economics in his market overview.

An update on the progress of TSV technology development in China was provided by Daquan Yu (Chinese Academy of Sciences – Institute of Microelectronics). Yusuf Leblebici (EPFL, Swiss Federal Institute of Technology) described their effort to build a multi-core 3D stacked processor using a unique TSV technology. Using a planar structure and optical “bridges” to connect “tiles” described by Cunningham was also a novel systems approach.

Like a large pile of Legos that could be used to create almost anything, there was a great deal of diversity presented in technology, approaches, and end products. The conference provided many insights into how and when 3D packaging will provide unique and differentiated products with greater performance at lower cost than products today.

Comments are closed.

%d bloggers like this: