Semiconductor Wafer Test Workshop 2015 Presentation – Are You Really Going To Package That?

June 24, 2015
Are You Really Going To Package That? - Ira Feldman and Debbora Ahlgren - SW Test 2015

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I had the pleasure of presenting “Are You Really Going To Package That?” at the 25th annual Semiconductor Wafer Test Workshop (SW Test / SWTW) on Tuesday June 9, 2015. Debbora Ahlgren and I took this opportunity to step back and look at how old paradigms in test-cell integration may lead to suboptimal solutions.

In an effort to reduce the cost-of-test (COT), a number of customers are increasing the parallelism of logic wafer probe cards. However, due to the complexity such as pitch and number of probes, the pricing for these cards is reaching astronomical levels. We do not believe this trend is sustainable, let alone logical. The presentation suggested examples of alternative solutions. It is clear that critical solutions need to be optimized at the test cell, factory, and supply chain level not just at the consumable (probe card) level.


IEEE Semiconductor Wafer Test Workshop 2014 Presentation

June 12, 2014
International Technology Roadmap for Semiconductors (ITRS) - Ira Feldman - IEEE SWTW2014

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At the 24th annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) on Wednesday June 11, 2014,
I had the pleasure of presenting “International Technology Roadmap for Semiconductors”. This presentation was co-authored with Dave Armstrong (Advantest) and Marc Loranger (FormFactor).

For the last fifteen years the International Technology Roadmap for Semiconductors (ITRS) has been looking fifteen years into the future. Based upon technology requirements and other inputs, ranging from the gate size of transistors to advanced packaging technology, the Test and Test Equipment Technical Working Group (Test TWG) has worked to develop the requirements for test technology and equipment.

The Test TWG is over seventy volunteers with deep technical expertise in test from around the world and from every sized company – Fortune 100 to individual consultants – and every type of company – semiconductor independent device manufacturer (IDM), fabless semiconductor, foundry, outsourced assembly and test (OSAT), automated test equipment (ATE) suppliers, prober, probe card, socket, handler, and more. Through Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop 2013

June 10, 2013
Ideal 3D Stacked Die Test - Ira Feldman - IEEE SWTW2013

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I had the pleasure of presenting “Ideal 3D Stacked Die Test” in Session Two “Industry Trends and Advanced Packaging Challenges” of the 23rd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) on Monday June 10, 2013.

Integrated circuits using 2.5D advanced packaging are shipping. 3D packaging with thru-silicon vias (TSV) has been demonstrated. “5.5D” packages may not be far behind. Probe card suppliers have made progress building interconnect technology for the micro-bump arrays. Standards committees have started defining IC interface standards and test access protocols.

But what does the Test Engineer and Management really want? What can they afford? What are the most likely scenarios? Factors that determine which test technology can support the desired test flow are examined. In particular, probe card technology for probing TSV bumps and potential usage models are reviewed.


IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

July 16, 2012

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Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is  Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

July 9, 2012

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Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

July 5, 2012

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Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were  Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)

July 3, 2012

Here are the highlights from Session Six “Meet the Challenge” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Robert Stampahar (SV Probe ‐ An Ellipsiz Company) and Wally Haley (Qualcomm), “Meeting the 1st Silicon: An Alternate Approach for Reducing Probe Card Cycles”:

Unlike other devices which can be tested in packaged form using a test socket, wafer level chip scale packages (WLCSP) rely completely on wafer probe cards for test. A load board with a test socket can usually be designed and fabricated quickly enough that the bring up and debug of new silicon designs is not delayed. When using a wafer probe card that contains a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer, the delivery of the probe card is  Read the rest of this entry »