IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)

Semiconductor wafer test workshop swtw sign

Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:

Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]

Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is performed between the wafer fabrication steps to verify the electrical properties of the just completed step. It s often called “in-process” testing. EOL of is verification of the overall electrical properties after the wafer is completed but typically prior to regular wafer testing which verifies device functionality. Quality and reliability – sometimes know as wafer acceptance testing (WAT) – if typically an extended testing, often under harsh conditions, to verify the  wafer properties.

All of these tests use special test structures – either located in place of a die on the wafer or more typically in the scribe lines (kerf or saw lines) between die. In the past, customers wanted to shrink pad size of test structures to reduce the scribe line width to allow more die per wafer. Now the trend is to shrink the pads to increase the number of test structures to increase the number of measurements sites per wafer.

One unique challenge of in-line test is that it often generates particles due to the unfinished wafer processing (not final metal or other possible pad contaminates) which may result in more defects than those being tested for. Sometimes the test engineer is given a fixed test time per wafer and needs to complete all the tests during that time. That’s why some customers want faster test times and higher test parallelism to fit more test within the allotted test time. Many have increased their parametric tests to 32 or 44 channels but very few have 48 total system channels – i.e. many systems are not fully populated.

In FormFactor’s experience, using microelectricalmechanical system (MEMS) probe cards has reduced test times up to 21% due to less frequent cleanings required and reduced retest rates by 5 to 14%. In addition, MEMS probes have increased the stability of the leakage measurements often measured in the femto- and pico-amp range.

With the impending transition to 450 mm semiconductor wafers, additional measurements per wafer will be required if there is a need to check for local variations across the wafer area. With the larger areas and the desire to make measurements faster there will continue to be a trend to increase the parallelism of parametric testing and the need for newer test equipment.

Questions:

  • What is the impact of the shift to laser cleaving which reduces the required width of the scribe line? Customers definitely want more data per wafer which requires more structures. The most likely place for these test structures is in the scribe lines. Therefore the ability to laser cleave may accelerate the move to even smaller pads to further reduce the size of the test structures and allowing the scribe line to shrink.
  • What drives parametric testing to 200 C or more? In-line processing is mostly room temperature between steps of deposition. At end of line it is not uncommon to see 80 C testing. Some of the automotive applications do drive lots of high temperature testing. FormFactor did an experiment with one customer at 200 C and couldn’t see the probe tips in the prober due to the heat waves off the wafer.


 

John West (VLSI Research Europe ‐ United Kingdom), “Trends in Test and Probe”:

Mr. West started with an overview of the broader semiconductor market in terms of capital expenditures (CAPEX), confidence, inventories, and utilization rates.

Most of the current CAPEX spending is upgrades for foundries, with the rest being spent on capacity upgrades for memory. VLSI Research has a subjective leading indicator they track called “Industry Confidence”. Industry Confidence is measured in degrees Fahrenheit to correlate to one’s own comfort. It is currently above 75 F so very good but not overheated. Semiconductor inventory is being well managed and the industry is getting very good at keeping utilization rate over 75% (definitely an improvement since 2000). Chip prices are relatively strong. All of these are good signs for the industry.

Even though there is a growing demand for devices, sales of automated test equipment (ATE) systems declined in the previous years and are predicted to remain flat moving forward. ATE companies have done a good job in reducing the cost of test and are the victims of their own successes. ATE for memory and system on a chip (SOC) devices have dropped significantly from 3% of device sales and have converged at about 1%. There has been significant consolidation in the ATE market with one dominant supplier in each market segment.

The cost of consumables, in particular probe cards and sockets, has grown rapidly while ATE costs have dropped. Since1997, probe card market revenue has had a 9% compound annual growth rate (CAGR) while the overall semiconductor market grew only 5.6%. Currently, 0.4% of semiconductor revenue us spent on probe cards versus 0.2% in 1997. Therefore probe cards and sockets are clearly in customer’s sight for cost reduction.

Why are costs per device tested not falling? The transition from cantilever to advanced probe cards doesn’t drive down the cost per device tested. And the average selling prices (ASP) of probe cards is not falling at the same rate as device ASP. There have only been a small level of consolidation from 60 to 50 probe card suppliers. And the historical top three companies have remained the same (with only a slight switch between MJC and FormFactor in 2011 revenue). For a market, it is also very unusual that no company has more than a 20% market share.

For 2012 Mr. West estimated that semiconductor revenue would be up 4% (total units up 7%), semiconductor equipment (CAPEX) revenue would be at least as good as 2011, ATE revenue down 6.5% to $2.5B, and semiconductor probe card revenue would remain “flat” at $1.2B.

Questions:

  • Wouldn’t cost of test calculated per transistor look better and be more accurate? Yes, it looks better that way. But test cost comes down to a percentage of the final price of the device being sold.
  • The price of advanced cards, such as those from FormFactor, have sky rocketed. However, they allow significantly higher parallelism on older test equipment thereby reducing CAPEX. Hasn’t this lowered the overall cost of test? Yes, there is a linkage. But ATE has done a good job in reducing cost of test, but probe cards will be hit next.


 

Andy Wee (GLOBALFOUNDRIES – Singapore), “Wafer Map Failure Pattern Recognition Using Artificial Intelligence”

As the wafer test process complexity increases, the amount of retest goes up due to either unstable or inconclusive test results. Sometimes the retesting of devices in an attempt to “recover” parts that have been incorrectly characterized as bad leads to the over testing of devices and an even greater loss of previously good dies. At the same time, there is the challenge of how to deposition a wafer based upon test results. One does not want to over test wafers nor throw away good wafers.

The disposition of a particular wafer often depends on the test engineer’s experience and knowledge base. GLOBALFOUNDRIES wanted to formalize this process and knowledge while increasing efficiency by using artificial intelligence (AI).

GLOBALFOUNDRIES built a database to clean and collect Standard Tester Data Format (STDF) test results from their wafer test operations. To this they added a modular system containing knowledge engineering techniques for each type of device. Currently, they have built three engines which look at the data using different techniques to provide disposition recommendations that are combined to produced a single output recommendation.

Currently the system can detect and flag underlying systematic problems. Though the accuracy is not yet sufficient to replace a human’s judgement, it is a good tool to assist the engineers and has clearly improved knowledge retention within the organization.

Questions:

  • How was the 83% accuracy of the system determined? A comparison between the tool’s output and the engineer’s final disposition was made.
  • What is the difference between this AI approach and other automated disposition approaches? Others are using “soft” bins based upon specific test results or other criteria. They have added pattern recognition not just fixed algorithms.
  • How do they optimize recommendations at the end of the flow in terms of should the parts be packaged or what grade of parts, etc.? Their system is only a recommendation to retest or not.

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