IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”

Pass or Fail? The Limits of Integrated Circuit Testing

Balancing test coverage versus test cost. What does a test failure mean? Value of yield increase

… and how it impacts your bottom line!

A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.

A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.

Continue reading “Pass or Fail? The Limits of Integrated Circuit Testing”