Category: Simulation

IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

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Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

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Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”

Thinking Big: $1 Trillion MEMS Market – Part 2

Part 1 described Janusz Bryzek‘s ambitious goal of a $1 trillion market for microelectromechanical systems (MEMS) that was the focus of the MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium. In addition, sensor swarms, road mapping and market numbers were covered. Challenges, example applications, and key takeaways are discussed here along with a final score card on the $1 T market.

Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 2”

Thinking Big: $1 Trillion MEMS Market – Part 1

Usual business advice includes thinking big to win big. Some organizations create Big Hairy Audacious Goals. Others like to find new markets that are underserved and grow to be number one. The semiconductor industry has Moore’s Law – the premise that the minimum cost point is achieved by doubling the number of transistors per chip every two years – driving it forward for almost fifty years.

Janusz Bryzek set a dramatic and ambitious goal of $1 trillion sales for the microelectromechanical systems (MEMS) market in 2022. Even though the MEMS market is expected to have “only” $12 billion in revenue in 2012, he isn’t being called a fool. Having cofounded eight seminal Silicon Valley MEMS companies and currently the Vice President of MEMS Development at Fairchild Semiconductor (which recently acquired his last company), Janusz is taken quite seriously.

Yes, at last week’s MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium there were some who  Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 1”

IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

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Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are Continue reading “IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)”

IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)

Here are the highlights from Session Eight – Area Array Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:

Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found.  However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)”

IEEE Nanotechnology Symposium – Session 7 – Nano-Enabled Energy II


Here are the highlights from Session 7 – Nano-Enabled Energy II from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Dr. David Predergast, Lawrence Berkeley National Laboratory (LBNL) Molecular Foundry, “Nature of Nano-Scale Interfaces and Mechanisms for Solar Energy Conversion.”