IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)

Here are the highlights from Session Eight – Area Array Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:

Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found.  However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping.

SV Probe performed experiments to investigate scrub and contact resistance (Cres) on copper pillar probes with and without solder (eutectic and lead-free) caps. They used their LogicTouch probe card architecture at 60 µm pitch and it can be scaled to 40 µm pitch.

They varied tip size and shape and used test wafers with 40 µm diameter pillars on a 60 µm grid. Cres (including path resistance of the probe cards) stabilized at 25 µm overdrive (OD) (~ 3 gF) at 1.3 ohms for both eutectic and SnAg caps.  There was no substantial difference between eutectic and SnAg solder caps. The Scrub mark disturbed area follows tip shape.  The scrub mark length and width was limited by either tip size or bump size. The smaller the tip, the deeper the scrub as expected.

When probing the copper pillar directly (without solder cap) the 9 µm width tips were stable at 50 µm OD (5-6 gF). However, the 12 µm wide tips had far worse Cres than 9 µm tips.  They concluded larger tips > 16 µm wide were effective for solder capped pillars to minimize damage to the solder cap.  For copper pillars (no solder cap), they need smaller tips (< 9 µm wide) for higher pressure to insure low Cres.

They also noted the bump height variation across the wafer was 10 to 15 µm (a substantial percentage of 25 to 50 µm overdrive) and they need to study the impact to the probe card design.

Questions:

  • Scott Lindsey / Aehr Test- Is the Cres data shown an average?  What is the scatter? Each plotted point is an average of 80 data points and standard deviation around 100 mOhm.
  • Stefano Felici / Technoprobe – Maximum current? Since fine pitch, 400 mA per probe.
  • Rey Rincon / Freescale – Temperature influences?  The main issue is when it is hotter, solder sticks more to the tips and becomes a cleaning issue.
  • ? – Do you need to reflow solder caps to avoid assembly defects?  Haven’t looked in to this yet.
  • ? – How to compensate for 10 to 15 µm global height difference?  Need to be absorbed by the OD.
  • Roy Swart / Intel – Noticed a 2 ohm difference between 9 & 12 µm tip widths on Cu what is the explanation?  Cres is not stable on 12 µm width and still dropping so probably not enough pressure.
  • Phil Mai / JEM America – Maximum compliance of probe?  Designed for 75 µm OD.

Denis Deegan, Analog Devices, “Contacting various metal compositions using ViProbe Vertical Technology”:

Joint paper with Simon Allgaier of Feinmetall.

They need to minimize pad damage due to probing (scrub mark size and depth) on known good die (KGD), Flip Chip on Lead (FCOL) and Over Pad Metallization (OPM) devices.  Since the ViProbe force versus displacement mechanism is non-linear (unlike Cobra & Cantilever) it is safer in terms of mark area and scrub depth since the force levels off. For these experiments they used a two ViProbe setup per pad to form a Kelvin connection to characterize Cres and scrub marks on different pad metals.

Aluminum (Al):  Analog Devices changed their solder bumping to electroplating which is overly sensitive to probe damage so they probe the Al pads on FCOL devices before bumping. Existing cantilever probes have a 0.8 µm scrub depth which sometimes is as deep as 1 µm.  Also when doing three temperature passes (ambient, -40C, 160C) they often break the pad edge due to thermal mismatch (CTE). The ViProbe had uniformly smaller marks with a tighter grouping well centered even at the temperature extremes with an average of 0.6 µm scrub depth.

Gold (Au): They are probing under bump metal (UBM) pads with a Au top layer on Embedded Wafer Level Packages (EWLP).  They are unable to make Kelvin contact (2 probes per pad) with cantilevers without punching through the Au final layer (~1 µm thick).  With the ViProbe they have 0.185 µm scrub depth and stable Cres of 0.52 ohm without cleaning (5K? touchdowns).

Copper (Cu) pad: Fritting (forcing 30 mA prior to measuring Cres) makes a slight improvement in Cres stability.  This is shown in red/blue circles on right side of chart on slide 34. Currently using Probe Polish every 1K TDs stable until 9 K TDs then the Cres deteriorates. Cu currently requires online cleaning to make stable measurements.  They also need to try online cleaning at temperature. The ViProbe technology is good but Cu is still challenging – and they need a longer term solution (better recipe or change in approach).

High Temperature: Feinmetall specifies the ViProbe to operate up to 150 C and Analog Devices regularly uses them at 160 C with success. For this test they pushed them further –the probes worked at 170 C but failed at 175 C.  As shown in a 2009 SWTW paper the Vespel head expands and probes fall off pads in probe card (i.e. the base of the probe no longer contacts the printed circuit board in the probe head).  To make progress they moved to a ceramic stiffener and think they can go over 200 C by adding a heat shield between head and PCB along with changing to a higher temperature PCB material.

High Speed sort:  Lastly they looked at high speed sorting of a 210 MSPS (million samples per second) Analog to Digital Converter (ADC).  Currently they have both Technoprobe and Microprobe cantilever cards that work for this product which is shipped in a packaged format.  They need to control the scrub marks for a KGD version (when the part is sold without a package) and would like a vertical solution. Denis showed the comparative performance between the cantilever probes and the ViProbe card.  Since the ViProbe card is a direct attach on a custom PCB the results turned out better than package test data. However the signal to noise ratio (SNR) test results identified an error in the PCB design termination that causes a harmonic – and the board needs to be corrected (shown in slide 51).

Questions:

  • Mark Ojeda / Spansion – What material did they use for 200C evaluation?  Used FR4 but only to evaluate the head. They need to switch to a higher temperature material for production usage.
  • Fred Taber / BiTS Workshop- What are the diamond shape pads shown in the pictures?  Pads are actually square – the diamond shape is tungsten plugs to give strength to pad.
  • Scott Lindsey / Aehr Test- 30 mA force current for Fritting what was the voltage clamp?  He doesn’t know.
  • Dennis / Taconic – They have high temperature materials. [Blatant sales pitch comment which almost won Dennis the “Golden Wheel Barrow” on the spot.]

Michael Huebner, FormFactor, “High Speed Control Bus for Advanced TRE”:

Tester Resource Enhancement (TRE) is FormFactor’s multiplexing of tester signals to test more than one device per “native” tester site. The demand for higher parallelism DRAM memory test has increased rapidly over the last several years.  Currently there is a need to test over 1,000 memory devices in parallel.  When increasing parallelism, you need to be careful to not increase test time when providing TRE.

The demand for higher integration required custom IC development which included control methods for Advanced TRE (A-TRE).  Advanced TRE has enabled x8 and x16 muxing of both I/O and control signals. And they expanding this to DC signals and power supplies

Their standard TRE has done well for last 7 to 8 years. However they need to move beyond x4 and x8 parallelism.  They also had done both DC-Boost for DC signals and PPS -TRE for the power supplies (x2) previously. However, they were running out of space for these as the number of devices under test (DUTs) increased.

It is conceivable to require 7,000 switches (relays) on a probe card – however they were running out of space, so they needed to design custom switches.  Also daughter card don’t make sense since the area of connector is as big as the switches.

Currently memory testers have at most only 256 control channels so they needed to build an A-TRE controller.  This allows muxing these 256 control channels which were originally designed to control one switch each to control all the circuitry on the probe card.  They developed two different busses as part of this architecture:

  • ProbeBus – a control and data bus that interconnects the A-TRE controller to all the resources (DC-Boot or A-TRE switch chips) on the probe card.
  • FormBus – interconnects the A-TRE controller to the tester.  Its first implementation is a wider bus (typical 18 bits wide) using slower control/utility lines of tester (normally designed to drive relays).   They are now developing a 4 bit bus using high speed tester channels (or dedicated tester resources) to increase speed and to enable data read back from the A-TRE controller.

Questions:

  • ?/Sandisk – when does multiple parallelism fail to scale? DRAMs are designed for everything to work in parallel.  With DC tests – maybe 15 seconds per die – do increases with parallelism.  Different issues with FLASH devices.
  • Mark Ojeda/Spansion – what about failures due to probes being on the edge [bead of the wafer and having the signals shorted]? They can introduce resistor isolation for control channels only.  DC signals can be disconnect with DC boost.  (They could implement this control based upon touchdown location.)
  • Stefano Felici  / Technoprobe – parts on main PCB or daughter cards?  They are still using some daughter cards but have a strategy to remove them. When the space for switch is the same as the connector there is no point using daughter cards.
  • ? – Expense of this approach?  Custom parts cheaper than other parts and by doing it the right way it makes the PCB easier. (PCBs are still 55 layers but they do not need to do sequential layer lamination.)

Matt Losey, Touchdown Technologies, “Low-Force MEMS Probe Solution for Full Wafer Single Touch Test”:

There are many challenges of a single touchdown probe card including resources, density, and routing.  But what about the probe card mechanics?  With 100K probes this is 1100 lbs at 5 gF/pin.

For their case study they looked at a “small” DDR3 1 Gb DRAM with 80 probes per die at 60 µm pitch and 1400 dies per wafer.  This is a total of 109,000 probes with a probe density of 1.7 / mm2. With their torsion probe design they can achieve pitches down to 50 µm for lead on center (LOC) pads and a probe density greater than 5 / mm2.  With x8 resource sharing they reduce 34 K input/output (I/O) signals to 10 K. And a majority of the probes are power and grounds.

In terms of the multilayer ceramic (MLC), 80 connections on the probe side is reduced to 60 on the tester side (mostly due to power and grounds).  And they can support 2 external pads per mm2 (so okay versus 1.7 probers per mm2).  However their MLC’s are 40 to 80 layers thick.  [Oh my…]  They build these in house and can control shrinkage tolerance since low temperature co-fired ceramic (LTCC) has less shrinkage than high temperature co-fired ceramic (HTCC).

The interposer between the MLC and the printed circuit board (PCB) has a signal density of 2.5 / mm2.  However, the interposers require frames and mechanics reducing the effective area so they are getting close to limit.

As to mechanical performance, one needs to look at probe card deformation under load using finite element analysis (FEA).  Another critical factor to look at is “retreat” (Session 5 & J. Caldwell at SWTW 2008) along with deformation.  To properly model mechanical load, one needs to first work with the probe design.

Matt examined typical probe force and compared several different styles of MEMS probes.  Touchdown’s torsional probe has two spring constant ranges (there is a knee in the curve, see slide 14).  They are roughly 2 gF at a target of 80 µm overdrive (OD). They also have ~20% engagement area due to angle of attack of their probes – so tip pressure is much higher therefore they need to reduce tip size.

With the current generation of testers, their modeling shows deformation that exceeds their limit (20 µm) if the probe force is > 2 gF/probe.  Therefore single touchdown with high pin count is difficult today unless the probe force is lowered (which may lead to contact issues).  Next generation testers have new interfaces with reduced “span” (mechanically unsupported areas) which produce acceptable deformation.  However, common probers still limited to 200 kgF thereby not eliminating need for even lower force probes for high probe count applications.

Questions:

  • ? – High pin count requires lots of interposer points with large forces.  Is the card flat enough? They added support throughout the array on latest designs.
  • Roy Swart/Intel – interposer force and contact resistance: have they done enough simulation?  Their suppliers have done that modeling – they assume a simple force versus deflection (so they don’t have a sophisticated non-linear model) for this interface.

Note: I will post the link for the slides once they become available.

One Response to IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)

  1. […] Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps” […]

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