IEEE Semiconductor Wafer Test Workshop – Challenges of RF Probing – Session Nine (Wednesday)

Here are the highlights from Session Nine – Challenges of RF Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Ellis Huang, MPI Corporation, “Novel Vertical Probe Card Solution for Multi-DUTs and RF Device on 3 GHz Applications”:

This project was done with UMC using MPI’s VPC vertical probe technology to test Bluetooth modules at 2.45 GHz.

In order to provide a 50 ohm signal as close to the device under test (DUT) as possible, they added dummy ground pins to the probe head around critical signal pins.  Even though these signal pins already had adjacent ground pads that were probed on the device, these dummy pins (probes) were positioned closer to the signal pin thereby maintaining the 50 ohm impedance.  The dummy pins are connected to other grounds via the copper flex circuit on the space transformer.

They also created a small enclosed (RF shielded?) area for the matching structures to tune the RF circuit on the tester side of the probe card.  Adjacent to this are the SMP connectors for attaching the high frequency signals.

Their regular VPC probe head has measured bandwidth of 1.5 GHz.  For this project they simulated the entire signal path then they built the hardware and characterized it with good correlation to the simulation using a fixed load. With a fixed 50 ohm load, they achieved a bandwidth of 3.3 GHz in the probe head and an overall bandwidth of 2.6 GHz.

Once they tested the probe card and probe head with the actual devices they needed to adjust the matching to avoid power loss. After adjustment, the total power loss of the RF signal path was ~ 1.5 dB and the bandwidth was just sufficient for 2.4 GHz testing.

Next they are working on upgrading the bandwidth of the VPC probe head from 3 GHz to 5 GHz.  And now that they have x4 DUTs working, they are working on a x8 DUT configuration for 2011.

Ryan Satrom, Multitest – ECT Interface Products, “High Frequency Solutions for Wafer Level Package Test”:

He showed their simulation of the entire high frequency signal path through the printed circuit board (PCB), the contactor based upon their new MER040 Pogo pins (spring on outside) in a ground-signal-ground configuration,  and the interface to the wafer level package (WLP) device.  Then he showed their measurements which correlated very well.

ECT is using simulation to build a comprehensive set of design rules for high frequency system design.  This will permit the cost effective construction of total solutions and help to avoid “over engineering”. As part of this effort they compared typical “rule of thumb” design rules for PCB design versus 3D simulation results. The two examples shown had a wide discrepancy between accepted rules and simulation results: stub drilling (required well below the ¼ wavelength frequency typically used as cutoff) and ground via proximity. They concluded that PCB design rules need to be based upon frequency and most basic rules work up to 500 MHz. Above 500 MHz you need to do simulation to generate proper rules.

Ryan also showed their proprietary tool for material and connector selection based upon configuration and frequency performance requirements. Putting all these elements together (simulation, design rules, and material selection) he showed several application examples of hardware built and measured to have the required bandwidth.


  • ?/MJC:  how to optimize the SMA connector bandwidth?  Major factor for optimization is the clearance of the signal to grounds in the layers of the PCB.

Note: I will post the link for the slides once they become available.

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