As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEESemiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.
As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”
Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.
Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEESemiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Here are the highlights from Session Eight – “RF Probing” of the 21st annual IEEESemiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
As the final presenter at this week’s IEEESemiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
Ellis Huang, MPI Corporation, “Novel Vertical Probe Card Solution for Multi-DUTs and RF Device on 3 GHz Applications”:
This project was done with UMC using MPI’s VPC vertical probe technology to test Bluetooth modules at 2.45 GHz.
In order to provide a 50 ohm signal as close to the device under test (DUT) as possible, they added dummy ground pins to the probe head around critical signal pins. Even though these signal pins already had adjacent ground pads that were probed on the device, these dummy pins (probes) were positioned closer to the signal pin thereby maintaining the 50 ohm impedance. The dummy pins are connected to other grounds via the copper flex circuit on the space transformer. Continue reading “IEEE Semiconductor Wafer Test Workshop – Challenges of RF Probing – Session Nine (Wednesday)”
Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:
Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found. However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping. Continue reading “IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)”
Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:
For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test. The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested. Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Seven (Tuesday)”
Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:
For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk. However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS). Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin. Continue reading “IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)”
Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:
Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing. A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications. Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test. These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards. Continue reading “IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)”
Joel presented an overview of inkjet technology and how they are applying it to printing circuits. They have developed a process that allows them to inkjet a catalytic ink which after UV curing allows the electroless (e-less) plating of copper. Given the choice of inkjet systems from scanning formats where the print head moves to fixed heads where the material moves past the head they have a wide range of potential substrate sizes and formats to choose depending on the end application. Continue reading “IEEE Consumer Electronics Society – Conductive Inkjet Technology”
Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual 
High Technology Business Development - Ira Feldman 