Riding Off Into the Sunset – BiTS 2013

March 14, 2013
Sunset over Phoenix, Arizona during BiTS Workshop

Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

July 2, 2012

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

June 28, 2012

Click image to download presentation

Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paperThe Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was  Read the rest of this entry »


Two Conferences – Two Industries Challenged By Post PC Era

March 15, 2012

Tim Cook introducing Apple's latest iPad

The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.

Even though many were surprised to learn that we are now “Post PC”, some of us who have been developing strategies for the electronic supply chain have Read the rest of this entry »


Silicon Valley Test Workshop – 2nd Year “Rocks”

November 28, 2011
2 5D? 3D? What? 3D IC Packaging - Ira Feldman

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Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

October 17, 2011

 

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)

October 14, 2011

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Seenew Lai, MPI,High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:

The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined Read the rest of this entry »