IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)

Here are the highlights from Session Four – Standards and Methods of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW).

Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:

Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing.  A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications.  Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test.  These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards.

One of the challenges is total probe count.  However, the recent increases are mostly power & grounds probes so they are still okay with 1800 signal channels.  However, as the quantity of probes increase so does the total applied probe force which for some cards has grown over 250 KgF.

Recent challenges of some of the new non-memory test systems have included:

  • Advantest T2000 RECT550

550 mm x 480 mm rectangular probe card.

Due to the large card size needed to change how the system flips the probe card over.

Each instrument has different connector pin-out and shields not always ground (sometimes signal or utilities) so need to be able to reconfigure interface.

  • Teradyne FLEX

440 mm diameter

Needed to add tall pogo blocks to allow for clearance of  parts on the backside of the probe card.

Total of 6400 pogos – all reconfigurable in the interface.

  • Verigy V93000 Direct Dock

Eliminated the probe card and the probe head mounts directly on the 600 mm x 480 mm load board.

System also has four point reference surface that needed to be accommodated.

Future challenges include:

  • Probe counts climbing further with a probe force of up to 500 KgF.
  • Higher signal counts over 12K channels.
  • More circuitry on probe card requiring additional real estate.
  • Customer desire to test probe heads independent of probe card.

Question: What is the maximum size round that they have done? 560 mm diameter.  Mark Ojeda from Spansion who asked said they are currently at 572 mm.

Matthew C. Zeman, Intel Corporation, “A New Methodology for Assessing the Current Carrying Capability of Probes used at Sort”:

Intel would like to increase the current carrying capability (CCC) of probes to reduce probe burn even as the pitch of probes decrease.  Last year Boyd Daniels the ISMI Probe Council Chair shared their procedure for CCC measurement. This standard is based upon two minute long current pulses which mimic steady state current. Intel has established their own methodology described in this presentation to better mimic their test conditions as an additional test procedure.

The Intel protocol is based upon using the spring constant (kprobe) as the ultimate metric since it is a fully controlled parameter of the probe manufacturer. To characterize CCC, Matt started with their single probe measurement tool and added electronics including a Chroma programmable current load to force and measure current. The Chroma unit is the heart of their setup since it allows the easily program the duration and cycles of the current load. Original their system didn’t take deflection of the system as the probes were loaded in to account. They figured out that they needed to measure how much overdrive (deflection of the probe) was actually being achieved for a given displacement of the test fixture.

They discovered that Contact Resistance (Cres) is a key parameter and that slight changes in Cres has a significant impact on measured CCC. With as small variation of a Cres as 100 mOhm, the lifetime reliability of a probe would vary as much as 10x at higher currents. Heat generation at the probe tip may be the #1 contributing factor to probe failures under current load.


  • Maybe merge with ISMI model? Both Matt and Boyd agreed that it would make sense to do so.
  • Can the point of failure under high current be moved?  Maybe make the failures occur on the space transformer? They have done some characterization of space transformer.  However, it looks like the probes are the limiter for high current.

Rehan Kazmi, SV Probe, “Measuring Current Carrying Capability (CCC) of Vertical Probes”:

SV Probe has also put together similar characterization equipment for CCC.  They have also been modeling CCC for beryllium copper (BeCu) probes.  Rehan shared some of their modeling results and experimental results.

They determined they need to keep the total stress which is a combination of the mechanical load and thermal load below the plastic deformation point of the probe material in order to avoid deforming the probe or reducing its height.  They also determined that a probe Can handle more current at the recommended overdrive (OD) versus maximum OD since there is less mechanical stress. In addition, CCC reduces as the wafer temperature increases.

Note: I will post the link for the slides once they become available.

One Response to IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)

  1. […] Rehan Kazmi, SV Probe, “Measuring Current Carrying Capability (CCC) of Vertical Probes” […]

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