Through-Silicon Vias (TSV) – High Technology Business Development

Chip Scale Review: The Three Most Important Words for 3D ICs?

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Continue reading “Chip Scale Review: The Three Most Important Words for 3D ICs?”

Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span Continue reading “Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

Silicon Valley Test Workshop – 2nd Year “Rocks”

2 5D? 3D? What? 3D IC Packaging - Ira Feldman — Click image to download presentation

Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Continue reading “Silicon Valley Test Workshop – 2nd Year “Rocks””

Semiconductor Packaging: 2.5D, 3D, and Beyond!

MEPTEC's 2.5D, 3D and Beyond Packaging Conference

The MEPTEC “2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.

Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with Continue reading “Semiconductor Packaging: 2.5D, 3D, and Beyond!”

IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)

Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:

Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Continue reading “IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)”