Silicon Valley Test Workshop – 2nd Year “Rocks”

Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has an exciting energy level missing in other forums. Beyond the greeting of old industry friends and colleagues, there was true participation and engagement. This was demonstrated in numerous ways from the dialogue between speakers and audience during the presentations to the in-depth discussions in the packed exhibit hall.

The 170 attendees were a good cross section of engineers and managers from almost all of Silicon Valley’s electronic companies. Presentations that really stood out were engineers talking about their test problems (not even “challenges”), airing their “dirty laundry” (possibly to their management’s chagrin). If you listen closely, these can be the most informative since they show real world challenges that companies are working hard to resolve.

Bill Bottoms kicked off the conference with his keynote “Test Challenges in the Era of More than Moore Technologies” providing insight into current and future test challenges. It is always exciting to see glimpses of the future based upon Bill’s work on the International Technology Roadmap for Semiconductors (ITRS). And he always has new photos of advanced technology worth knowing about.

The morning session focused on Design for Test with Al Crouch (Asset Intertech) presenting “I-JTAG Test Strategy for 3-D Chip Packages“, Steve Pateras (Mentor Graphics) presenting “DFT Trends in the More-than-Moore Era“, and Douglas Kay (Cisco Systems) presenting “Bridging the Structural/Functional Test Gap“. After lunch with considerable interaction between the attendees and exhibitors, the conference was split into two tracks: “Test Methods” and “Interface Hardware”.

Jerry Broz (International Test Solutions) started the Interface Hardware track with “Assessing CRES Performance for On-line Cleaning Optimization” an excellent review of how to systematically optimize the probe card cleaning process to balance device yield versus operational costs.

My presentation “2.5D? 3D? What? An overview of 3D IC Packaging and Test Challenges” followed. It addressed the motivation behind and the basic process flows of building stacked integrated circuits (ICs) including test implications. I also reviewed how the different organizations are addressing the challenges of developing stacked ICs along with some of the wafer probe solutions under development. Hopefully, it will serve as a good primer on the test technology issues and stimulate the discussions necessary to drive the development of production worthy solutions.

Phil Warwick (R&D Circuits) then presented “25 GB/s Socket and Loadboard Test Issues“. Phil discussed many issues that can no longer be ignored now that there has been a significant increase in the operating frequency of devices along with some unique PCB fabrication methods for addressing them. In “Pulse Current Test Considerations for Contacts“, Gert Hohenwarter (GateWave Northern) reviewed the challenges in simulating and measuring the performance of contacts when they are subjected to very high current pulses. Jim Brandes (Multitest) next presented “Kelvin Contacts – A Tutorial” discussing the basics of Kelvin measurements along with typical applications. Michael Giesler (3M) finished the track with “Impact of Embedded Capacitance on Test Socket and Test Board Performance” showing the application of 3M’s Embedded Capacitance Material which can be used for the construction of both printed circuit boards (PCBs) and test sockets.

The Test Methods track also had six papers presented. I wished I could have also attended since three of these papers were written by former Hewlett-Packard / Agilent / Verigy co-workers of mine. The papers presented were:

• “Testing a Complex USB3.0 SOC Device“, Albert Alcorn (Cypress Semiconductor)
• “Embedded DRAM: Test Challenges and Methods“, Craig Soldat (Cisco Systems)
• “Testing High Speed Memory Interface: A case for FPGA based Test Systems?”, Mathieu Duprez (MuTest)
• “Concurrent Test Method for Test Time Reduction in Production of Mobile Devices“. Amir Owzar (ST Ericson)
• “Broken Scan Chains Routinely Debugged with New Optical Technique“, Cathy Kardach (DCG Systems)
• “RF Loop Back Testing Concepts and Results“, Bob Bartlett (Verigy/Advantest)

Once again, a hearty thanks to Nick Langston for producing the Silicon Valley Test Workshop, the exhibitors for funding it, and everyone who participated! I’m definitely looking forward to next year’s event.