Wow! The Burn-in and Test Strategy (BiTS) Workshop just turned 15! The world of semiconductors has certainly changed over the years. And the BiTS Workshop has kept up with what is “Now & Next” in the burn-in and test of packaged integrated circuits (ICs). These achievements were celebrated in style by the more than three hundred participants at the recently held 2014 BiTS Workshop in Mesa, Arizona.
Don’t pop the champagne just yet! Although plenty of good news was shared at the 2014 SEMIIndustry Strategy Symposium (ISS) there was the sobering outlook of possible limited long-term growth due to technology issues as well as economic projections. Noticeable was the lack of news and updates on key industry developments.
This is the yearly “data rich” or “data overload” (take your pick) conference of semiconductor supply chain executives. The majority of the attendees and presenters are from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. Keeping the pressure on for advanced technology were the “end customer” attendees and presenters – semi-conductor manufacturers.
Cost! Cost! Cost! are the three most important words for 3D semiconductors.
Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.
Market adoption is increasing rapidly for wafer level packaging (WLP) as it is applied to a greater range of applications. The shift of “Post-PC” from desktop to mobile devices has driven the development of WLP into the mainstream by providing extremely space efficient and low cost packaging. There has and will continue to be many technical and business challenges in packaging devices on wafer (or other substrate) en masse instead of on an individual basis.
Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
What’s in a name? A lot! A name itself might not mean much but it can trigger expectations and stereotypes. In the United States we have red states and blue states depending on which political party has the majority vote. Similarly, when someone labels themselves on the basis of their political party affiliation (Republican, Democrat, Libertarian, Independent, etc.) others Continue reading “Coupling & Crosstalk: Name Calling”
Integrated circuits using 2.5D advanced packaging are shipping. 3D packaging with thru-silicon vias (TSV) has been demonstrated. “5.5D” packages may not be far behind. Probe card suppliers have made progress building interconnect technology for the micro-bump arrays. Standards committees have started defining IC interface standards and test access protocols.
But what does the Test Engineer and Management really want? What can they afford? What are the most likely scenarios? Factors that determine which test technology can support the desired test flow are examined. In particular, probe card technology for probing TSV bumps and potential usage models are reviewed.
Attending the SEMIIndustry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.
The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.
Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI InternationalTechnology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.
Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:
Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.
Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:
Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).
This year’s IEEESemiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.
Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.
Some consider the many of billions of dollars invested in the semiconductor supply chain to be huge bets on yet to be proven technology and future business. Even if you take a strict view of this as simply business it is possible to learn something from gambling.
The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.