IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

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Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were evaluated for probing over active active area (PoAA) on CuP. Mechanical performance characterized included: probe force versus over drive, probe mark quality versus over drive, damage to active circuitry under pads, and lifetime. The probe mark quality was good and the mark area remained less than the limit of 50% of the area of the pillar to ensure package reliability. Contact resistance (Cres) stability, cleaning, and test repeatability where evaluated in terms of electrical performance. Low Cres(consistently below 2 Ohms) was maintained with on-line cleaning every 200 touchdowns using lapping film.

Additional analysis was done to verify that the co-planarity of the pillars remained within specifications after being contacted by the probes. Intel’s packaging reliability standard requires the co-planarity to be less than 20 um between the seating plane (three tallest bumps) and the shortest bump. 3D automated inspection of 100% of the pillars was performed on three wafers prior to first probe then after one, four, and eight touchdowns. Each wafer was run at a different level of overdrive (40, 60, 100 µm) and was probed eight times. After all probing was complete, the maximum pillar change was less than 10 µm from the original co-planarity.

What remains to be completed is the PoAA analysis to make sure there isn’t any cracking under the pad and to finish the extended life testing to more than one million touchdowns.

Questions:

  • If the pillar height is reduced, how do you check for pillar cracking? There is no specification on pillar cracking. But based upon experience there shouldn’t be a problem. They will check for hidden cracking below the pad and will look at the pillar too.
  • Since these parts have a large array of pillars for power and ground it is assumed one doesn’t need to connect to all of them. If the number of probes is reduced, what level of current will need to flow through the pillar? And will Cres change due to electro migration, etc.? Nothing along these lines has been seen. Due to the end applications,  the current requirements aren’t very high.
  • Besides co-planarity analysis was there any further reliability or other testing on damage to Cu pillar? No there has not been any testing beyond that described.

 

Todd Tsao (ASE Global ‐ Taiwan) and Senthil Theppakuttai (SV Probe), “Advanced Cu‐Pillar Applications at 50 µm – Enabling Fine Pitch Probing”:

Next generation flip chip interconnects for 2.5D & 3D packaging will use copper pillars that are 25-30 µm in diameter and  25-30 µm in height. These bumps will require probing in arrays at 40 to 50 µm pitch.

A feasibility evaluation using a SV Probe card to probe these pillars was made using a custom test chip designed by ASE. The test chip had copper pillars configured in a daisy chain in a 50 µm array. This test chip was designed prior to the current Wide I/O memory standard was defined (which has the bumps on a 40 µm x 50 µm array).

In a 50 µm array configuration neither a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer is feasible since via on pad construction is required. However, SV Probe’s MST technology can be built at this pitch. The guide plates for this vertical (buckling beam) probe card are produced using micro-electro-mechanical system (MEMS) processing. Since the guide plates have a smooth and polished surface finish, an anti-reflective treatment was added so that the wafer prober can see the probes. 

Contact force of the probes is 2.5 gF at 50 µm for over drive. The preferred operation range is 20 to 40 µm over drive to keep the force below 2 gF to minimize pillar damage and high enough to provide stable Cres. The data shown indicated good planarity, tip alignment, and low Cres (3.2 ohm max, 1.7 ohm average). Probe mark inspection was run after two touch downs on a wafer and passed inspection. Additional tests to characterize electrical, mechanical, and thermal performance are being performed at ASE.

Questions:

  • Was the probing performed on thinned wafers which will be used for 3D packaging? This work was done on engineering wafers of standard thickness.
  • What was the assembly yield prior to probing and after probing? Was any difference seen? This is part of the follow-on work.
  • Are the probe tips square and flat? Yes.
  • Are crown tips possible? These are MEMS probe and only 2D shapes can be built at this size.
  • Was the maximum resistance of 3.2 ohms measured with a probe card metrology tool? Was there any detailed resistance tests performed? Yes the measurement of 3.2 ohms was on a metrology tool. No, no detailed resistance measurements were made yet.
  • What is the current carrying capability for the product and for the probe? It is 250-300 mA for probes as a function of the board level. A lower over travel will increase the current. ASE has not completed their full characterization yet.
  • What is the maximum test frequency? This has not yet been characterized and will be done later.

 

Raphael Robertazzi (IBM Research), “Test and Measurement Challenges for 3D IC Development”:

The development of 3D packaging includes new challenges in design, process, and test. Mr. Robertazzi and colleagues have been focusing on the challenges of test. In particular, how to obtain test access either through direct access (i.e. electrical probing of the part) or logical access using test vectors.    

Typical failure modes from the wafer processing and assembly processes unique for 3D packaging include open through silicon vias (TSVs), solder bridge faults, TSV leakage to the silicon wafer, and resistive micro-bumps (where the C4 flip chip solder is significantly thinner than desired). Electrical measurements to sense these defects require greater than 12 orders of magnitude from 1 mOhm to 1GOhm. Therefore, true four-point (Kelvin) source measurement units (SMU) will be required in future very high parallelism test heads. To test early devices, IBM developed a special interface to connect a high precision SMU (Agilent 34980A) to a standard automated test equipment (ATE) tester for high speed digital vector delivery.

Since there is no IBM qualified probe technology for fine pitch micro-C4 bumps placed atop the TSVs (used to connect the die in 3D packaging), the team needed to find another approach to look for die defects in singular die prior to stacking. Current injection testing was selected to find leakage paths especially in the die cache areas. Using traditional vertical probe cards, at pitches significantly larger than the TSV pitch,  IBM was able to probe floating aluminum pads which were over the active circuits. These probes were then used to inject current to find leakage paths through the device. The team proved the concept and demonstrated there was no significant damage to the active circuitry beneath the probe pads.

IBM’s existing wafers probers don’t work very well on singulated chips. So, IBM had Tokyo Electron (TEL) build a diced chip tray to hold singulated dies for probing. This tray is quickly configurable for different sized dies as needed. The tray has greater thermal resistance than a standard wafer chuck, however this is not an issue on the current designs.

Questions:

  • What were the 3D testing requirements and is there data to show? IBM does not permit them to to talk about yield and performance. There were two recent papers at the Integrated Solid-State Circuit Conference (ISSC) – one was on embedded dynamic random access memory (DRAM) and the other was a clocking paper – that may provide additional information.
  • Does the custom chip tray require custom prober software? In single contact mode, which they use, it is not required but the standard software is inconvenient. TEL does offer additional software to support it better.

 

Chang-Hoon Hyun (Samsung Semiconductor Institution Technology), “An Analysis of Probing CRES in Gold Bumping Pad Using Automatic Test Equipment”:

Awarded Most Inspirational Presentation

Samsung has discovered that as the size of the gold bump goes down, the device yield goes down dramatically due to wafer probe issues of opens and bump damage. The opens are a result of high Cres which are due to a smaller number of contact points since the probe tip is smaller (fewer asperties or a-spot within the smaller tip area) and the formation of a titanium (Ti) oxide layer. The titanium oxide is formed by the hydrogen peroxide H2O2 etching of the titanium-tungsten (TiW) under bump metal (UBM) below the gold bump.

The behavior of the titanium oxide on gold bumps is similar to that of aluminum oxide on aluminum pads. As the number of probe touchdowns increase, the Cres increases. And like aluminum oxide, titanium oxide can be cleaned off the tips to restore the contact resistance. Since the cleaning media is abrasive this reduces the life of the probe. Using rhenium-tungsten (ReW) tips Samsung has to clean every 35 touchdowns, resulting in significant probe card lifetime reduction. And the cleaning increases the test time by 30 to 40 minutes for each wafer.

To find a better probe material platinum probes were compared to the default rhenium-tungsten ones. The rhenium-tungsten start with a low Cres but increased over to time as the titanium oxide increases. Whereas the platinum probes have higher Cres from the start but remain stable over 100,000 touchdowns. The behavior of both probe metals are explained by looking at the work function. As the difference between the work function of the pad and the probe increases, so does ohmic heating which increases the need for cleaning. Platinum is therefore a better choice for a probe since metals with work function closer in value result in significantly fewer cleanings. 

Additional work will be performed to determine how to best reduce or remove the titanium oxide to reduce the Cres. In addition, a similar study will be undertaken for devices with solder bumps.

 (No questions.)

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