IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)

Here are the highlights from Session Six “Meet the Challenge” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Robert Stampahar (SV Probe ‐ An Ellipsiz Company) and Wally Haley (Qualcomm), “Meeting the 1st Silicon: An Alternate Approach for Reducing Probe Card Cycles”:

Unlike other devices which can be tested in packaged form using a test socket, wafer level chip scale packages (WLCSP) rely completely on wafer probe cards for test. A load board with a test socket can usually be designed and fabricated quickly enough that the bring up and debug of new silicon designs is not delayed. When using a wafer probe card that contains a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer, the delivery of the probe card is usually gated by the time to build the space transformer. Typical delivery times for new designs of MLCs and MLOs can be on the order of ten to twelve weeks resulting in probe cards deliveries close to the twelve week mark.

At the same time, “direct attach” probe cards that use a vertical probe technology (directly attached to a printed circuit board (PCB)) have greatly increased in complexity as the pitch between probes has decreased and the number of test sites have increased. This complexity has increased design and fabrication time of the PCBs. Delivery time for these probe cards are now running at approximately nine weeks.

To solve these challenges, SV Probe has developed the Modular Space Transformer (MST) architecture. The PCB is generic and can be designed and fabricated in advanced. For each new device design, the MST and probe head are reconfigured and built to order. The MST is mechanically connected not soldered to the PCB. Using the MST, SV Probe is able to deliver probe cards in six weeks alleviating the delays with related technologies.

Other advantages of the MST include significantly lower path resistance (compared to a standard MLC) and additional components (such as decoupling capacitors) can be placed inside the MST closer to device under test (DUT). At the same time, the MST supports a higher density of signals to avoid skipping die sites between DUTs (i.e. allowing “brick wall” configurations). Probe heads without skips typically permit a more efficient stepping pattern as shown by an example sixteen site probe head, similar to those that are in production, which went from 82% to 92% stepping efficiency when the skips were removed.

Questions:

  • What is the minimum pitch of the MST and what is inside the MST? The minimum pitch that can be supported today is 50 µm. There are spring pins between the MST and PCB, and a copper based low resistance interconnect inside the MST.
  • In the data shown which type of part has the highest resistance? The MLC resistance value was calculated based upon trace resistance and the number of vias (each averaging 2 ohms).

 

Gert Hohenwarter (GateWave Northern, Inc.), “Fine Pitch High Performance Needle Probe Concept Using Novel Micro-Plating Technique”:

Using MicraMetal’s Microjet plating system, conductive bumps can be formed and placed without photolithography. Embedding wires in a dielectric and flattening / shaping form the basis for a high frequency probe when the Microjet system places bumps at the end of each wire. The Microjet system can place copper, nickel, platinum, gold, and rhodium so the appropriate tip material can be selected per application. One advantage of this technology is only the X & Y placement accuracy of the bump is critical. Once the bumps are placed, the probes can be planarized as a group for increased Z accuracy.

An example probe was shown that had the tips at a 200 µm pitch with 10 µm tall bumps. This prototype was characterized in terms of resistance versus force, force versus displacement, insertion and return loss, and time domain transmission. The loss and time domain measurements were both simulated and measured with good correlation.

This prototype showed that this approach is feasible for constructing lower cost high frequency probes that are customized to the end application in terms of contact metal and device pad pitch. Future steps are to improve the radio frequency (RF) performance, develop the rest of the assembly, and attempt to build a by four probe head.

Questions:

  • Will the unfinished measurements be updated in the SWTW program archive? Yes, if the results turn out well, joked Mr. Hohenwarter.
  • What is the minimum pitch this technology can achieve? 100 µm is achievable today. With additional development work, finer pitches should be achievable.
  • What material was selected for the probe body? Either tungsten or beryllium – copper (BeCu) will be used for the final material.
  • What is the maximum height of a bump? The tallest MicraMetal has grown is 100 µm. Bump height is a function of cost and speed.
  • What is the minimum tip size achievable? As small as 20 µm has been achieved today at the base of the tip. The tip base can be made smaller but a radius to the tip will remain.


 

Rey Rincon (Freescale Semiconductor) and Stefano Felici (Technoprobe USA), “Improved Cantilever Probing ‐ Minimizing Scrub Marks”:

Freescale is moving legacy devices from gold wire bonds to copper wire bonds to reduce costs. Since these are legacy devices, the devices share bond and probe locations (i.e. both are done on the same pad).  Copper wire bonding however is more sensitive to pad damage than is gold.

At the same time, Freescale would like to save costs for new product introduction. With multiple device designs often sharing a development wafer with possibly several design revisions, probe cards with high non-recurring engineering (NRE) charges such as vertical or advanced technology have become prohibitively expensive.

To solve these challenges, Technoprobe’s no-scrub cantilever technology was evaluated on the Freescale C90 silicon on insulator (SOI) pad design. A design of experiments (DOE) matrix evaluating the number of repeated touch downs and differing amounts of overdrive was run on a test wafer to determine the level of inner layer dielectric (ILD) damage. At the same time, probe performance was examined in terms of tip wear, probe mark size, and probe mark depth. WaferWoRx probe mark inspection and analysis on over 25,000 pads was also performed on the wafer.

Measurements on the probe card before and after wafer test showed only a slight increase in probe alignment error accompanied by a slight increase in tip diameter. However, the probe planarity significantly improved. All are consistent with “breaking” a new cantilever probe card.

Once a suitable overdrive value was determined for the probe technology, a two wafer kappa study was performed to compare the Techoprobe probe technology to the existing plan of record probe cards. Bin flipping (changing of performance levels within specifications) of 2.1% was well below the 6% permissible maximum. The yield difference between the cards was 1.8% nearly half of the 3% limit.

Freescale will continue to evaluate this card for long term stability. If it performs well, Freescale will obtain two cards with the no-scrub technology to test actual product. Since the card has 575 probes per die, they will quickly obtain large data sets.

Mr. Felici shared that the demise of cantilever probe cards has been greatly exaggerated as demonstrated by this new Technoprobe technology. A general rule of thumb is that the pad size should be larger than 3x the tip diameter for a cantilever probe. With 50 µm x 50 µm pads and smaller pads becoming common, there is a greater need for smaller tips and no-scrub probing. This probe technology is rated for 1.5 M touchdowns (TD) and they have had units that have reached 1.6 M TD in the field.

 (No questions.)

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