3-D Microstructures – High Technology Business Development

IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)

Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:

Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.

The IBM team adapted a burn-in board system to Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)”

IEEE Nanotechnology Symposium – Session 5 – Nano-Processes

Here are the highlights from Session 5 – Nano-Processes from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6^th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Dr. Hans Stork, VP and CTO Applied Materials, “Nanotechnology in Semiconductor Industry.”

Important to look at market trends. However for an equipment manufacturer, need to look at wafer volumes (area) more than unit volumes due to die shrinks.

Continue reading “IEEE Nanotechnology Symposium – Session 5 – Nano-Processes”