IEEE Nanotechnology Symposium – Session 5 – Nano-Processes


Here are the highlights from Session 5 – Nano-Processes from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Dr. Hans Stork, VP and CTO Applied Materials, “Nanotechnology in Semiconductor Industry.

  • Important to look at market trends.  However for an equipment manufacturer, need to look at wafer volumes (area) more than unit volumes due to die shrinks.
  • In general logic (microprocessors) consumes the smallest area.  DRAM is 5x the area of logic.  And FLASH is 5x the area of DRAM.
  • Process development typically starts in logic then moves to DRAM & FLASH.
  • See his slides for some of the best SEMS I have seen that illustrate the definition of nodes for DRAM & logic (gate width, etc.).
  • Double UV pattern exposure will probably get the industry down to 20 nm.
  • Can do lots with optical equipment & additional processing – but it add significant costs.  For example at 45 nm – it requires 7 layers interconnect for simplest devices / functions.  More complicated devices require even more layers.  As process nodes shrink, more layers are required.
  • Applied technology will enable FinFET (around 15 nm) – where the transistor structure is standing on the side.
  • On-chip optical interconnect – discussed for decades.  Adoption will be a function of distance – probably for connections over 1 cm due to cost (power & space) to convert electrical to optical and back again.
  • E-beam based inspection to find defects < 30 nm.  Hard to detect defects optically at this scale.  Once again see the slides for great defect SEMs.  However, throughput is not as good on E-beam or SEM inspection compared to optical inspection due to operational issues (need for vacuum, scan rate, etc.).
  • Moore’s law: 0.7x scaling MPU/HP Logic every 2 years.  10 nm node around 2017 via multiple litho options in development. Need to develop new structures, materials & unit processes to support this scaling to 10 nm.

Question:

In the post CMOS world – will Moore’s law slow down? A: In general no.  But a slowing down the adoption of the most advanced features.  CMOS will remain the back bone of the electronics industry – so he doesn’t see a post CMOS world.  An analogue is he doesn’t think we will drive electric cars – we will simply drive electrically enhanced cars with gas engines…

Dr. Mike Stuke, Prof. Max Planck Institute, “Laser-direct-write creation of free-standing 3D structures and some biotech applications.”

  • Typically need precursors to build 3D structures – something that is both volatile & stable.  I.e. it needs to be formable but can take a set.  Then the material is disassociated in to something left to be the structure and something that goes away (scaffolding or form).  Example in slides is how the Eifel tower was built with support than removed – same with 3D structures.
  • However Laser-CVD can grow structurse locally without supports in the gas phase at 50 um/s rate.
  • Showed example of tweezers that are activated when a laser beam irradiates one side of a “wishbone” causing it to expand which in turn moves the tip.
  • Then an example of a linear micromotor where the laser hits 1 or 2 legs of a tripod to expand and move structure. Micromotor indexes bar over 5 um steps.
  • Built micro-cages for tracking & capturing nano particles in solution using ring electrode structures.  Voltage, frequency & amplitude control where in the cage the particles are held so they can selectively store particles.

Really good videos of these in operation – however I doubt they will be posted to the website….

Dr. Joy Cheng, Research Staff Member, Lithography Materials Group, IBM Almaden Research Center – “Nanofabrication: bottom-up meets top-down.”

  • Using bottom-up fabrication, sub 10 nm pitch is achievable.  Chemical contrast can be used to pattern materials, increase surface area or make arrays of holes.
  • IBM has also made air gap dielectrics this way.
  • Directed Self-Assembly (DSA) – a combination of top-down + bottom up fabrication. Critical Dimensions (CD) is fundamentally controlled by molecules in any process – hence the advantage of bottom-up.  And this avoids the need for new expensive tools – just buy the polymers.
  • Two approaches:
    • Graphoepitaxy – use topography to contain polymer patterns (hard masks).
    • Chemical Epitaxy – surface chemistry to guide.
  • Chemical Epitaxy can achieve:
    • Frequency multiplication
    • Also does pattern rectifications – CD of pre-pattern is not critical – adjusts to desired pattern
    • Defect tolerance
  • Hitachi disk platter example: using E-beam pattern bump on a 79 nm pitch grid.  Then using Chemical Epitaxy achieve bump on a 39 nm final grid.  So achieve 4x the density at the same time reduce the E-beam time required.o Very high volume manufacturing:  10^13 islands (bump) per disk and 10^9 disk platters per year at a total cost < $5 per disk platter.  [Think about that: 10^24 bumps per year for one company and one product technology. Also note $5 x 10^9 = $5B, however the disk market was only $35 B in 2008 so may need to do a sanity check on market share and COGS here…]
  • Discussed work to extend Optical Lithography using DSA and integrating in to existing 193 nm tools on their line.  Example shown takes 30 nm lines on 100 nm pitch and builds them up to a structure with 25 nm pitch lines.  Achieves a 4x tighter pitch.
  • In previous process node transitions from 45 to 32 to 22 nm they were able to keep Mask Error Enhancement Factor (MEEF) and Exposure Latitude (EL) at acceptable levels.  However, with 15 nm these jumped to unacceptable CD levels.  Showed examples of how DSA brings both MEEF & EL back to acceptable levels.

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