Coupling & Crosstalk: Testing the Supply Chain

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2018 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Testing the Supply Chain

Much the same as the world, test is not simply black or white but varying shades of grey and a jumble of colors. Test has continually responded to semiconductor technology challenges to provide the right solutions. As a result, the organizational placement and “supply chains” for test have rarely been neat or tidy. Is Wafer Test a “front end” or a “back end” function? Are the lines between wafer probe and final test solutions and the suppliers blurring?

Electronic test began as simple go or no-go quality “gauge” measurement. Either the component or product was good enough to move to the next production step or it failed. Failed items would be reworked where possible – for example by swapping or adjusting a subsystem in a product. Or discarded when rework was not possible.

As a go/no-go check the concept of test is relatively simple. But the situation quickly becomes challenging and expensive when all the details are taken into account. Test costs are always higher than desired especially when test is misconstrued as a necessary but non-value-add activity. Once its true potential was discovered, test quickly became a cost-saving measure and a revenue enhancer for many semiconductor devices. Not only can test reduce costs by avoiding additional processing and consuming materials on units that are defective, it can enable rework of defective units before it is too late. And test provides the data necessary for continuous improvement in upstream processes to increase yield and in downstream processes to enhance margin.

In certain high value devices, test identifies devices with higher performance enabling sales at a higher margin since the cost to produce is the same for all units. For example “performance binning” of microprocessors identifies the premium units to sell at a higher price hence increasing both revenue and margin. And many semiconductors would not yield at all without repair due to their complexity and large size. (Larger die are more likely to have defects since each fabrication process has a fundamental number of defects per square area.) Dynamic random access memory (DRAM), flash memory, and field programmable gate array (FPGA) devices all require test to identify which areas on the die need to be swapped for spare memory or logic cells. Without test the intrinsic yield and hence revenue of these devices would be almost zero.

In the quest for greater cost savings and operational efficiency, semiconductor test itself has become more complicated. Over a generation ago the two main test steps were “Wafer Sort” and “Final Test”. Wafer Sort tested each device (die) on a wafer to determine which were good enough to be assembled into a packaged part (semiconductor die are mounted or encapsulated into the package). After the testing was completed, the wafer was cut apart to singulate the die (wafer saw) with only they good die ending up in packages. Due to the limitations of existing wafer probe technology this testing was often very rudimentary. Since many devices could not be run at speed in full operational mode typically only gross defects were found. Eliminating the clearly bad dies avoided the cost of the package, which for some high-end devices could cost as much as producing the die. After packaging, the part was tested again at Final Test to ensure there were no manufacturing defects and that the part operated to its full specifications. Final Test data also provided the “binning” to identify premium parts and repair cell based devices.

More recently a large part of Final Test has migrated to Wafer Test (often renamed from Wafer Sort to reflect the change) enabled by advances in probe card technology. Newer probe cards have enabled exercising many devices closer to or at speed and often in massively parallel configurations for cost considerations. Today whole DRAM wafers containing hundreds of memory devices are regularly tested simultaneously. This change has further reduced operational costs by eliminating weak devices earlier, performing cell-based repair in bulk, and simplifying the handling of devices at wafer rather than as individual parts during test. Final Test is still performed to provide the test coverage that cannot be accomplished at Wafer Test and to ensure the packaging operation has not introduced defects. Even though the amount of test time spent at Final Test may be reduced and the tests simplified, Final Test of a packaged part is still essential.

The recent introduction of wafer level chip scale packaging (WLCSP) has also shifted how testing is performed. WLCSP and other advanced packaging – in fan-in and fan-out configuration – forms the “finished” package on a substrate. The substrate may be the original silicon wafer that the die were fabricated on or a temporary substrate on which previously tested good die are placed. The package interconnect and “encapsulation” are processed onto the substrate along with the die. The resultant shift is that the devices are tested while still on wafer/substrate before singulation. And this testing typically contains all the items previously covered by the Wafer Test and Final Test steps. For some devices, all the testing can be performed in one step eliminating additional test steps.

This advanced packaging shift has produced new test solutions with more in development. The most common approach is a hybrid Wafer and Final test cell configuration. For wafer based WLCSP devices, a wafer prober is used to handle the wafers but the electrical contact to the automated test equipment (ATE) is not made with a “traditional” probe card. Today the dominant contactors are built using miniature spring pins and socket technology more frequently supplied by traditional socket vendors than traditional probe card suppliers. The spring pins are coming out ahead due to the lower cost and robustness at the required connection pitch compared to vertical probe card technology which is better suited to finer pitches. As a result, there is a growing disruption in the supplier base blurring probe card and socket companies as WLCSP technology increases in volume.

The drive for higher performance and end-product differentiation has increased the demand for multi-die packages. In particular, Heterogeneous Integration (HI) is placing multiple die with different functionality into the same package to enable newer and higher performance solutions. Numerous advanced packaging approaches such as 2.5D, 3D, fan-out wafer level packaging (FoWLP), and others have been developed to support HI. Fan-out based packaging is currently dominating leading-edge high-volume applications such as smartphone processors providing the right mix of cost and performance. Fan-out packaging using wafer (FoWLP) and panel (FoPLP) substrates are now in production. The panels are significantly larger than wafers – some as large as 600 mm on a side – in order to further reduce cost per unit. Clearly panel sized equipment has been built for the processing of panels even though panel-sized test equipment has not been widely seen. Initially panels are being cut into smaller sizes to fit onto existing wafer probers and there will be a transition to panel-based handlers (probers?) for future test cells once there is sufficient demand. It is not yet clear which existing test equipment suppliers – probers or handlers – or which outsider(s) will be the winning vendors. And similar to current efforts to standardize panel size(s), we may be far away from standardized test interfaces for this new equipment.

A detailed optical inspection of each die is performed after singulation to identify any cracking, chipping, or other damage that may have occurred during the dicing or sawing process. However, this is not sufficient for high-reliability devices where it is essential to fully test after all operations are completed especially singulation. And there are other devices that cannot be tested in-situ on a substrate due to constraints such as neighboring devices or the need for non-electrical stimulus. For parts such as these, new solutions such as test-on-strip are being implemented to provide high parallelism test of devices in advance packaging. It remains to be seen if there are enough high volume applications to provide a sufficient return-on-investment for these new solutions.

Constant changes in test solutions – including technology and suppliers – are essential to keep up with the new product challenges. The proper strategy based upon the right market information is required to successfully navigate the dynamic world of test. Be sure to have the proper perspective to ensure that you are managing change instead of being managed by change.

As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance.