SEMI ISS 2014 – Scaling Innovation

Courtesy of Ivo Bolsens (Xilinx), SEMI ISS 2014
Courtesy of Ivo Bolsens (Xilinx), SEMI ISS 2014

Don’t pop the champagne just yet! Although plenty of good news was shared at the 2014 SEMI Industry Strategy Symposium (ISS) there was the sobering outlook of possible limited long-term growth due to technology issues as well as economic projections. Noticeable was the lack of news and updates on key industry developments.

This is the yearly “data rich” or “data overload” (take your pick) conference of semiconductor supply chain executives. The majority of the attendees and presenters are from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. Keeping the pressure on for advanced technology were the “end customer” attendees and presenters – semi-conductor manufacturers.

The official theme was “Pervasive Computing – An Enabler for Future Growth” and the presentations made it clear that pervasive computing will greatly increase the demand for semiconductors. However, as discussed in context of very high volume applications such as the Internet of Things and the recent TSensors Summit, such explosive growth will only occur at a sufficiently low price point for these semiconductors and micro-electromechanical systems (MEMS) based sensors.

A major focus of ISS is economics: both the global trends that drive the semiconductor industry and the cost of new technology. Unlike past years, much of the discussion about new technology centered on economics rather than “will it work.” Past discussions about 450 mm wafers, extreme ultra-violet (EUV) photolithography, and 3D transistor structures focused on the soundness of these technologies, not the economics.

The question that is being asked of technologists with increasing frequency is: “When will Moore’s Law end?” The cost reduction necessary to keep pace with Moore’s prediction that the minimum cost per transistor will be achieved when the number of transistors on a semiconductor device doubles every two years has primarily been achieved through shrinking the size of the transistors (“scaling”). Many smart people predicted the end of transistor scaling was upon us, hence the demise of Moore’s Law, only to be proven wrong as scaling continued.

Numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved. Rick Wallace (KLA-Tencor) reminded us that the demise of the Concorde supersonic plane was the economics and not the technology. In drawing a parallel to the challenge of continued scaling, Mr. Wallace said, “Moore’s Law is more likely to be killed in the board room than in the laboratory.” Therefore, we really need to look to the product managers and executives as well as the technologists for the answer.

The development on 450 mm silicon wafers continues via the G450C consortium and Paul Farrar (G450C) provided a progress update. Their current estimates show 450 mm ready for production in the range of late 2017 to mid-2020. Meanwhile Bob Johnson (Gartner) showed projected mid-2018 intercepts for Intel and Taiwan Semiconductor Manufacturing Company (TSMC) capability and first true production fabs in 2019-2020. Many of the equipment companies expressed concerns about their return on investment (ROI) for developing 450 mm equipment especially with a limited market. The weakness of demand can be summed up by Manish Bhatia (SanDisk) who said SanDisk/Toshiba didn’t want to build the last 300 mm fab nor were they in the running to build the first 450 mm fab. It appears as though many customers and suppliers share a “wait and see” attitude even though there are still many years of hard work required to launch 450 mm.

No formal update on extreme ultra-violet (EUV) photolithography was presented this year although concerns about throughput and cost were mentioned by several speakers. These concerns are part of the fundamental economics of scaling which will require EUV and/or multi-patterning (multiple passes through the photolithography patterning modules for each layer of the semiconductor device instead of the single pass typical of older process nodes) to achieve smaller dimensions. ASML’s last presentation to ISS was in 2012 shortly before they became the “sole” developer of EUV so I hope there will be a public update later this year. For a while, EUV appeared to be a prerequisite for 450 mm development based upon process node intercept but the G450C plan of record (POR) is 193 nm immersion photolithography. G450C will start “investigating” EUV in the second half of 2016. Is this another code for “wait and see”?

Ivo Bolsens (Xilinx) reviewed the challenges and costs in developing next generation application specific integrated circuits (ASICs) and application specific standard product (ASSP). In particular he shared the staggering increase in the cost of the non-recurring engineering (NRE) to develop leading edge semiconductors. (Shown in the chart above.) In less than three years, the estimated NRE cost has jumped from $85 M for a 45 nm design to over $170 M for 28 nm. Included in these NRE estimates are the cost of the design work, masks, embedded software (IP licenses), and yield ramp-up cost. The data presented shows an exponential growth for NRE for each new process node. Rough extrapolation would place 14 nm at $340 M and 7 nm at $680 M respectively. Good news, scaling will continue. Bad news, products may not be able to afford it.

With all this dark and murky news about the future, what was the good news from SEMI ISS? Innovation. The undercurrent of almost every presentation was: since we cannot guarantee that future scaling will provide the savings needed, we need to look at alternative materials, device structures, computation models, system architectures, etc. to continue on the expected cost reduction slope. The list includes a wide range of technology from “More than Moore” (system in packaging, 2.5D, 3D packaging, etc.) to 3D FinFET transistors to carbon nanotubes (CNT) to optoelectronic interconnects, and beyond.

Mr. Wallace in his opening keynote discussed the prerequisites for innovation and shared his concern that some companies have become “too big to innovate”. Even more importantly, if the semiconductor industry wants to remain relevant and attract the best young talent we need to be the “magic behind the gadget.” The Tuesday afternoon sessions closed out with Mark Randall (Adobe Systems) who described his efforts to drive grass-roots innovation by empowering any employee to innovate with no strings attached. Young Sohn (Samsung Electronics) provided his keynote “Innovation in a Connected World” at the banquet describing their work to move from communication devices (smartphones, tablets, etc.) to something that does more to improve lives.

Yes, “innovation” has become an industry buzzword that is often overused. Having seen where these companies say they need to go it is clear many understand it is time to innovate or die. They realize that profitable scaling won’t last forever. Difficult strategic decisions need to be made – marketers and engineers cannot / will not change the direction of their companies by themselves. Enabling innovation and making bold strategic changes requires executive leadership.

Meanwhile, consumers will expect the continuation of Moore’s Law  – or at least the end result of continually lowered cost and/or higher performance – without giving a thought to the industry’s inability to continue cost effective scaling or other technical mumbo-jumbo. We still need to continue to make the magic happen!

As always, I look forward to hearing your comments directly. Please don’t hesitate to contact me to discuss your thoughts.


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