Semiconductor Wafer Test Workshop – High Technology Business Development

Semiconductor Wafer Test Workshop 2015 Presentation – Are You Really Going To Package That?

Are You Really Going To Package That? - Ira Feldman and Debbora Ahlgren - SW Test 2015 — Click image to download presentation

I had the pleasure of presenting “Are You Really Going To Package That?” at the 25th annual Semiconductor Wafer Test Workshop (SW Test / SWTW) on Tuesday June 9, 2015. Debbora Ahlgren and I took this opportunity to step back and look at how old paradigms in test-cell integration may lead to suboptimal solutions.

In an effort to reduce the cost-of-test (COT), a number of customers are increasing the parallelism of logic wafer probe cards. However, due to the complexity such as pitch and number of probes, the pricing for these cards is reaching astronomical levels. We do not believe this trend is sustainable, let alone logical. The presentation suggested examples of alternative solutions. It is clear that critical solutions need to be optimized at the test cell, factory, and supply chain level not just at the consumable (probe card) level.

IEEE Semiconductor Wafer Test Workshop 2014 Presentation

International Technology Roadmap for Semiconductors (ITRS) - Ira Feldman - IEEE SWTW2014 — Click image to download presentation

At the 24th annual IEEE
Semiconductor Wafer Test Workshop (SWTW) on Wednesday June 11, 2014,
I had the pleasure of presenting “International Technology Roadmap for Semiconductors”. This presentation was co-authored with Dave Armstrong (Advantest) and Marc Loranger (FormFactor).

For the last fifteen years the International Technology Roadmap for Semiconductors (ITRS) has been looking fifteen years into the future. Based upon technology requirements and other inputs, ranging from the gate size of transistors to advanced packaging technology, the Test and Test Equipment Technical Working Group (Test TWG) has worked to develop the requirements for test technology and equipment.

The Test TWG is over seventy volunteers with deep technical expertise in test from around the world and from every sized company – Fortune 100 to individual consultants – and every type of company – semiconductor independent device manufacturer (IDM), fabless semiconductor, foundry, outsourced assembly and test (OSAT), automated test equipment (ATE) suppliers, prober, probe card, socket, handler, and more. Through Continue reading “IEEE Semiconductor Wafer Test Workshop 2014 Presentation”

IEEE Semiconductor Wafer Test Workshop 2013

Ideal 3D Stacked Die Test - Ira Feldman - IEEE SWTW2013 — Click image to download presentation

I had the pleasure of presenting “Ideal 3D Stacked Die Test” in Session Two “Industry Trends and Advanced Packaging Challenges” of the 23rd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) on Monday June 10, 2013.

Integrated circuits using 2.5D advanced packaging are shipping. 3D packaging with thru-silicon vias (TSV) has been demonstrated. “5.5D” packages may not be far behind. Probe card suppliers have made progress building interconnect technology for the micro-bump arrays. Standards committees have started defining IC interface standards and test access protocols.

But what does the Test Engineer and Management really want? What can they afford? What are the most likely scenarios? Factors that determine which test technology can support the desired test flow are examined. In particular, probe card technology for probing TSV bumps and potential usage models are reviewed.

IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

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Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

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Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

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Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)

Here are the highlights from Session Six “Meet the Challenge” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Robert Stampahar (SV Probe ‐ An Ellipsiz Company) and Wally Haley (Qualcomm), “Meeting the 1st Silicon: An Alternate Approach for Reducing Probe Card Cycles”:

Unlike other devices which can be tested in packaged form using a test socket, wafer level chip scale packages (WLCSP) rely completely on wafer probe cards for test. A load board with a test socket can usually be designed and fabricated quickly enough that the bring up and debug of new silicon designs is not delayed. When using a wafer probe card that contains a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer, the delivery of the probe card is Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

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Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

Road-to-450-mm-Semiconductor-Wafers-Ira-Feldman-SWTW-2012.png — Click image to download presentation

Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)

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Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:

Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]

Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)

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Here are the highlights from Session Two “Optimizing Probe Depth Performance” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Tommie Berry (FormFactor, Inc.), “Actual vs. Programmed Over Travel for Advanced Probe Cards”:

As the number of probes on a probe card increase, the total force required to compress these probes – know as probe force – is increasing. With high force the actual over travel (AOT) – also know as overdrive – of the probe is often significantly different than the programmed over travel (POT) programmed in the prober. Even though memory test engineers with very high probe count cards have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)

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Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers

The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.

My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.

I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.

With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.

IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Continue reading “IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)

Here are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Seenew Lai, MPI, “High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:

The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined Continue reading “IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)

Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Kevin Fredriksen, SPA GmbH, ”MSO – Multi-Site Optimizer”:

Most wafer probers do not supply intelligent stepping algorithms to calculate the most efficient sequence of moving the wafer relative to the probe card. (Ed: At the core of this is a traveling salesman problem.) The situation is exacerbated when Continue reading “IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)

Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:

Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.

The IBM team adapted a burn-in board system to Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Spring Pin Probing – Session Five (Tuesday)

Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:

Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Continue reading “IEEE Semiconductor Wafer Test Workshop – Spring Pin Probing – Session Five (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)

Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:

Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Continue reading “IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)”

IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are Continue reading “IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)”

IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”

IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)

Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:

Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.

One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.

Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)”

IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)

On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.

Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:

Dr. Chen started with Continue reading “IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)”

Probe Card Cost Drivers from Architecture to Zero Defects

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As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.

Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.

Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.

There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.

I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.

Silicon Valley Test Conference – Something New & Overdue

Starting off something new is often challenging and difficult with many unknowns. Kudos to Nick Langston for creating the Silicon Valley Test Conference that was held last week. (November 8 & 9, 2010) It was the first test conference to actually take place in Silicon Valley. And yes there were some minor “bugs” like registration delays and a no-show by the audio visual contractor that should be solved in next year’s Rev 2.0. Even with a few rough edges, the quality of the presentations and the exhibitors shined through to make this a success.

The conference opened with an excellent keynote address by well-known industry expert Continue reading “Silicon Valley Test Conference – Something New & Overdue”

IEEE Semiconductor Wafer Test Workshop – Challenges of RF Probing – Session Nine (Wednesday)

Here are the highlights from Session Nine – Challenges of RF Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Ellis Huang, MPI Corporation, “Novel Vertical Probe Card Solution for Multi-DUTs and RF Device on 3 GHz Applications”:

This project was done with UMC using MPI’s VPC vertical probe technology to test Bluetooth modules at 2.45 GHz.

In order to provide a 50 ohm signal as close to the device under test (DUT) as possible, they added dummy ground pins to the probe head around critical signal pins. Even though these signal pins already had adjacent ground pads that were probed on the device, these dummy pins (probes) were positioned closer to the signal pin thereby maintaining the 50 ohm impedance. The dummy pins are connected to other grounds via the copper flex circuit on the space transformer.
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IEEE Semiconductor Wafer Test Workshop – Area Array Probing – Session Eight (Wednesday)

Here are the highlights from Session Eight – Area Array Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 9th.

Senthil Theppakuttai, SV Probe, “Probing Assessment on Fine Pitch Copper Pillar Solder Bumps”:

Flip chips devices are shrinking from 150 µm to 35 µm pitch interconnect. At 150 µm pitch solder balls formed by deposition or electroplating, and stud bumping are typically found. However at tighter pitches down to 35 µm, copper (Cu) pillars with solder caps are the preferred termination. The copper pillars solve electro-migration issues and mechanical/thermal (CTE) mismatch found with solder balls and stud bumping.
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IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Seven (Tuesday)

Here are the highlights from Session Seven – Probe Potpourri of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:

For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test. The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested.
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IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Jay Thomas, Grund Technical Solutions, LLC., “Probe Cards with Modular Integrated Switching Matrices”:

For the last 30 years, most scribeline parametric testing has been approximately 85% Current-Voltage (I-V) testing and 15% Capacitance-Voltage (C-V) testing. For these types of tests a 10 MHz bandwidth switch matrix has been sufficient.

However, some of the larger fabs such as HP, IBM, and Intel have started performing pulsed Current-Voltage (PIV) and electrostatic discharge (ESD) testing. These customers started this type of testing about four years ago unknown to Agilent & Keithley (the two largest DC parametric tester suppliers). This PIV and ESD testing requires high frequency switch matrices with 1 GHz bandwidth. [For more about ESD testing please see Jay’s second presentation below in this session.]
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IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:

For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk. However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS). Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin.
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IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)

Here are the highlights from Session Four – Standards and Methods of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW).

Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:

Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing. A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications. Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test. These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards.
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IEEE Semiconductor Wafer Test Workshop – Improving Cost of Ownership – Session Three (Monday)

Here are the highlights from Session Three – Improving Cost of Ownership of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Rey Rincon, Freescale & Jeff Greenberg, Rudolph Technologies, “Optimizing Test Cell Performance Using Probing Process Analysis and Predictive Scrub”:

Rey summarized efforts at Freescale to improve test cell performance with multi-tier cantilever probe cards by investigating prober performance, probe card performance and probe card analyzer correlation to the test cell.
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IEEE Semiconductor Wafer Test Workshop – High Temperature Probing – Session Two (Monday)

Here are the highlights from Session Two – High Temperature Probing of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Keith Breinlinger, FormFactor, “Addressing the Operating Challenges of Full Wafer Contactors”:

Keith started by providing a real good analogy of the challenge of wafer probing in terms of contacting the edge of each sheet of papers in a sixteen high foot stack. He used the new full wafer probe cards SmartMatrix (DRAM) and the TouchMatrix (NAND FLASH) as the basis of his presentation.
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IEEE Semiconductor Wafer Test Workshop – New Contact Technologies – Session One (Monday)

Here are the highlights from Session One – New Contact Technologies of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW)

Jay Kim, Western Specialty Technologies, LLC, “New Probe Card Architecture – Ceramic without MLC”:

He showed how Fine Instrument Co., Ltd. (Korea) built a new probe card architecture which eliminates using multi-layer ceramics (MLCs) to avoid the cost and lead times issues.
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IEEE Semiconductor Wafer Test Workshop – Opening Session (Sunday)

The 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) started this evening. Rumor has it that attendance is over 240 this year which is a vast improvement over last year’s 160 or so attendees. At the peak the conference had almost hit 600. Things started off well with a reception where I had the chance to catch up with many industry friends and colleagues.

After dinner, Jerry Broz the General Chair kicked things off with the “Probe Year in Review”. In summary:
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