IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)

On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.

Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:

Dr. Chen started with a review of semiconductor history pointing out that the fundamentals of wafer probe have not changed much since the development of the wire bond in 1967 and C4 flip chip technology in 1970. However, as predicted by Moore’s Law, which was basically a promise that semiconductor technology will get cheaper over time, semiconductors have become both cheaper on a per transistor basis and more complex in terms of total number of transistors.

He then discussed that the current driver of the semiconductor life cycle is one of “Information” – i.e. search engines, machine-to-machine communication, etc. And the next driver will be “Life Sciences” including biotechnology and green energy. In the current “Information” stage, there is not only a significant growth in semiconductor device volumes but an even larger growth in data traffic.

At the same time the packaging technology demands of these new devices are “divergent”:

  • Smart Phones & Tablets: WLCSP combined with PoP, Thin Packaging
  • Networking: Large die Flip Chip, Ultra Low Alpha, networking IC specific packaging

He then discussed more Moore (the continuation of Moore’s law below 20 nm and beyond CMOS), More than Moore (how to interact w/people & environment), and the combination of SOC & SiP to form higher value systems. For example, our hand size dictates the size of a smart phone but we want to put more functions in it. Therefore, we need to figure out how to shrink everything including the digital components, analog circuitry, and integrated MEMS sensors.

In the 1990’s there were a few types of standard packages since the volume driver was the personal computer (PC), which has a defined architecture. However, today there is a tremendous proliferation in packages because there are now all types of new devices with lots of innovation driven by the market. He then discussed the accompanying changes in the backend (the process of packaging semiconductor devices for assembly into products) as driven by both economics and the requirements of these products. For example WLCSP in 2000 was too small to handle and too expensive. Now in 2011, 40 to 60% of iPhone parts are WLCPs.

Dr. Chen then examined the challenges of SiP and 3D packaging along with the challenges of wafer probing these packages. Some example architectures he showed included a Frauhofer camera module, a Xilinix stacked silicon interposer FPGA, and a MIT Tera-scale Computing Module. These devices showed how additional functionality such as power savings and optical interconnect were achieved using these new packaging schemes.

In his view, 3D interconnect is best thing since sliced bread. However, there are serious logistical and financial business challenges that accompany this. Today test can clearly identify if a semiconductor die (bare device from a wafer) is good prior to packaging and if it is still good after packaging. This allows a fabless company to compensate fabrication and packaging suppliers based upon quantity of “good die” that are processed. However, with 3D packaging it is extremely difficult, if not impossible, to determine if the die is bad or if the packaging is defective if test only occurs after stacking all the die. Therefore, this technology will drive new business models both for the integrated device manufacturers (IDMs) and the fabless companies.

In response to questions he added:

  • Reconstituted wafers from WLCSP fan out are processed in a similar fashion to a regular wafer. However, there will be significant probing challenges since the redistribution layer will extend beyond the die with no silicon underneath portions that will contain some of the probe pads.
  • Proliferation of packaging types will continue since the market is driving different products. And the market is the determining the package type versus PC with fixed architecture. For example the iPad functions like a netbook – but inside it is totally different. In the past people wouldn’t accept new package types – but now they are far more willing to be different in order to achieve product differentiation.
  • Stacking of memory parts on top of microprocessors will continue. Solving the thermal issues is of vital importance since the heat needs to be dissipated to permit the proper operation of these parts. Lots of time will be spent on these issues. And how are we going to probe stacked memory wafers with similar or worse thermal issues when multiple stacks are powered up at once?

His final remarks: IEEE is our “professional home” and it is important to have this workshop to develop the technologies used by the industry. Technology innovation builds on and requires a knowledge base that continuously grows. At our conference there are lots of people from the supply chain but not from the universities. Without additional academic participation, where is the future knowledge growth going to come from?

2 Responses to IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)

  1. […] discussed in Dr. Chen’s keynote address, Embedded Wafer Level Packaging (eWLP) is a new type of wafer level chip scale packaging (WLCSP). […]

  2. […] dominant computing platform. I started using the “Post PC” term mid-last year after William Chen’s keynote at the IEEE Semiconductor Wafer Test Workshop (SWTW) discussed the proliferation of semiconductor […]

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