Probe Card Cost Drivers from Architecture to Zero Defects

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As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.

Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.

Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.

There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.

I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.

 

2 Responses to Probe Card Cost Drivers from Architecture to Zero Defects

  1. andrei berar says:

    Interesting and realistic. There are a few things that may not be obvious, but have huge impact on the Probe Card costs:
    Design methodology – standardization of expensive components is crucial
    Layout optimization (specially for # sites < 20) : define the layout based on minimum # of touch downs and constrains . Every extra touch down adds to cost of test
    Maintenance & Repair costs

    Optimize overall test cost vs. "localized" cost optimization

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