IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

 

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring many touchdowns. For example, some of their Flash memories have upwards of 3,000 dies per 200 mm wafer. Even with a tester with 144 sites, this might require over 21 touchdowns due to resource limitations whereas some larger Flash devices can be tested as one touchdown on a 300 mm wafer.

With “ghosting”, one device under test (DUT) site on the probe card is connected in parallel to another site typically on opposite side of the probe array. This may be done for several pairs of sites. In the basic version, one of each pair of sites is in contact with a DUT while the other site is not in contact with the wafer based upon the stepping pattern. A more advanced version uses relays to switch between each site in a pair. Ghosting allows more flexibility in the shape of the probe array to improve how the probes map to the actual wafer thereby reducing the number of touchdowns required.

In the examples shown, one or more touchdowns were saved per wafer using ghosting. These reductions of 8 – 12% touchdowns translate directly to lower test time per wafer. Of course, this approach won’t help with only 1 touchdown per wafer. There needs to be approximately 4 to 20 touchdowns to gain from this approach. Even with ghosting, there may be 2 or 3 dies per wafer that cannot be tested without adding additional touchdowns. With very large die counts per wafer, it is probably more cost efficient to skip and scrap these dies. With a larger number of dies that cannot be reached, say 30, one needs to consider closely if they should be skipped or additional touchdowns added.

Since relays take up too much area on the probe card, for future designs they are looking for electronic switches that can switch all the signal & power for a die site.

Questions:

  • How much complexity does this add to probe card analyzer maintenance? One needs to supply all the information for both the metrology and the floor technician. Otherwise this will fail on the tester side and the technicians won’t understand why.
  • Who is the master of the test cell – tester or prober? The tester.

 

Larry Levy, FormFactor, “Challenges of CIS High Parallel Test“:

It surprising there hasn’t really been any detailed discussion about testing CMOS image sensors (CIS) at SWTW. Not only is there is substantial growth – driven by multiple cameras in smart phones and new automotive applications – there are also significant probe challenges.

The typical test flow has three wafer sort steps: light, dark, and logic. During the light test a calibrated light source is used to illuminate the CIS with different color light to measure response. The dark test looks at imager noise when no light is applied. Integrating light sources into the test head through the probe card present challenges. And the probe card itself needs to be designed to minimize the reflection of light and to not block the light path to the sensor array. For some applications it is necessary to embed lenses in the probe card to focus the light source.

With the growing volumes of CIS, multisite testing is required. And the shape of the test array has a significant impact on the the number of touchdowns required per wafer directly impacting the cost per unit tested. Previous multisite testing has be done with linear or diagonal arrays due to probe card limitations. With more advanced probe card technology, square arrays with skip row and skip column are possible providing significant (60 – 70%) reduction in number of touchdowns.

In addition, higher definition video with higher resolution requires higher speed CIS which in turn results in the need to move more data faster. This need for higher bandwidth requires high speed test including higher frequency probe cards. In the long term the probe card can probably carry the increasing data rate but the device may not support long rise times. Die shrinks tend to keep the die size the same since the area is dominated by the sensor. With each new process technology node, the size of each pixel is smaller. This permits increasing the number of pixels to increase the resolution of the CIS while keeping the die size the same.

In the past most CIS had bond pads on two sided pads. Current parts are moving to pads on three sides. With pads on three sides or a fourth partial side there is unopposed force from the probes so it is critical to use lower force probes to avoid pushing probes off the pads.

Noise pattern tests are sensitive to power supply levels. Placing capacitors near probes to reduce loop inductance is advantageous. As pixel size decreases there is less light collection per pixel requiring greater noise sensitivity and longer test time. With smaller pixels, greater care is needed to reduce particle generation since the particles may block one or more pixels resulting in the CIS failing the tests.

Questions:

  • What is the largest size area that “pupil” lenses can be integrated into? The largest array they have built so far is 32 sites with the area inside 100 mm. Each lens is individually adjustable. However FormFactor does not have the ability to adjust the lenses, they need to be adjusted on-site on the tester.
  • What percentage of parts require “pupil” lenses? It is becoming more and more common.  May not get to 70% but will be significant percentage.
  • What is the pitch size of the pads? That is an interesting question. With the usage of high speed serial interfaces they had assumed there would be a reduction in the number of pads to be probed. However, it turns out that the number of pads has stayed fairly consistent or gone up slightly. There are often several pads on a tighter pitch of 100 um or slightly less. Then there are other areas of the die with larger gaps between pads.

 

Ira Feldman, Feldman Engineering,Probe Card Cost Drivers from Architecture to Zero Defects“:

 

For a summary of my presentation please see here.

Questions:

  • At our company [a semiconductor manufacturer] we have standardized our probe heads so that they are interchangeable. However as soon as you innovate you are different so how can you standardize? For actual probe technology and architecture innovation will indeed make them different. But there are many areas where we could standardize as an industry. For example the format of input data. With all the different formats used the data subject to interpreation. What does this Korean character mean over here? Others take the input form from one company and rip off the logos and email it out to other probe card companies. One person told me of a case where they misinterpreted the design file data and built the card incorrectly. They had to quickly rebuild the card at their own expense. With a standardized format the data would be unambiguous. This would allow probe card companies to build software tools to drive their metrology and design systems.
  • Based upon what you’ve seen, what is one area where we should start standardization? Different companies will have pain points, therefore they will want to start in different places. As a group we should propose areas to start and solicit industry inputs to see where there is the greatest interest. It will require much work across the industry with the support of many to achieve.

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