IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)

Here are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Seenew Lai, MPI, “High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:

The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined that the cantilever probe was the largest contributor to the loss of bandwidth.

MPI developed the U+ cantilever probe which is built with an impedance matched coaxial structure. The coaxial wiring also runs out to the pogo pad instead of through the printed circuit board (PCB) (at least on the unit shown). Simulation and measurement data shows they achieved 2.5 Gbps and 51 ohm impedance for LCD large panel testing at less than 30 µm pitch.

Question:

• What is the design and function of the small (“daughter”) PCB? Is it due to the probe size difference or is a tight pitch PCB? (Ed: either declined to answer or didn’t understand the question.)

 

Takashi Sugiyama, Hitachi Chemical, “High Density and High Speed Approach for Probe Card PCB“:

Higher signal density and bandwidth necessary to support high speed devices are becoming difficult to achieve with traditional printed and etched multi-layer board (MLB aka as PCB). In particular, with high layer counts the maximum thickness of the PCB is also a limitation. Hitachi developed a multi wire board (MWB) process of placing individual wires in layers to form the interconnect instead of traces.

A video of the machine placing the wires was shown. It looks “like a sewing machine” in many ways. The wires are insulated so they can cross over other wires without significantly increasing the thickness of the PCB. And the wires provide lower signal resistance and cross-talk versus traditional multi-layer boards. Since the wires are not etched liked traditional traces, they also provides low conductor loss with a smoother surface and constant conductor width. Low conductor loss in turn improves signal integrity. Lastly, data was shown on the effectiveness of back drilling to remove signal reflection due to the stub of the plated through hole via. (True for both MWB & MLB.)

Questions:

• Are there design tools for MWB? Hitachi has their own design software. They do the routing from a net list.
• What is the cycle time and cost comparison to a MLB/PCB? MWB is 3.5 weeks including designs versus 10 days for MLB. MWB cost is slightly higher due to the special equipment. Average price is $10K for MWB versus $8-9 for MLB.
• How do you connect a pad on the top layer to a wire? Inside the board you don’t need a pad since the wire connects directly connect to thru hole. [Ed: this means you don’t need annular ring around the via.] This via is then connected to a pad on the outside of the board.
• Smallest pad pitch on an outside layer? 40 or 50 µm perhaps.
• I only see 90 & 45 degrees wiring. Can the system do other angles? Maybe in the future.

 

Cristian Gozzi, Technoprobe, “Electromagnetic Analysis and Verification of Probe Card Performance for First Pass System Success“:

With the demand for short lead times, typically 4 to 6 weeks, for high frequency probe cards it is becoming critical that the card work correctly the first time. There is insufficient time to build prototypes or to debug a card. Therefore, it is is advantageous to use using high frequency (HF) simulation to address all issues prior to manufacturing of card.

It is important to control both signal and power integrity. Without both, the probe card is unlikely to work properly at the desired speed. Step by step examples of the individual simulations performed for both the signal chain and power distribution were shown. A 3D electromagnetic field solver with very complex full mesh is used for the probes and probe head. While a 2.5D solver is used for the PCB to speed up simulation.

One of the specific benefits of the power supply simulation is to enable the careful selection of decoupling capacitors. In the example shown, the designer was able to go from over 100 decoupling capacitors to less than 30. The new capacitors selected provided the same electrical performance while the drastic reduction in quantity allowed more room for signal routing.

Question:

• How much extra time should be added to a project for the analysis required? There are two kinds of analysis. Some of the analysis is not directly linked to a specific design – it is more general knowledge – so it can be done in advance (pre-layout of a specific design).  Design specific layout, typically done after the layout of the PCB traces, doesn’t take more than 2 or 3 days if using a library of prior system and probe analyses. This analysis per design layout is simplified by using the 2.5 D simulation for the PCB.

 

Phil Hsieh, MPI, “An Advanced Cantilever Probe Card with 6 GHz Bandwidth for RFIC Wafer Testing“:

Most cantilever probe cards cannot operate correctly over 100 MHz, so MPI developed their U+ probe technology. This presentation covered additional simulation and characterization of the U+ probe technology discussed earlier in this session. The specific application shown was for radio frequency integrated circuit (RFIC) testing.

Questions:

• The stated customer application was at 3.8 GHz. Have there been any applications closer to the 6 GHz? The technology should work up at 5 [sic] GHz.
• Has it been deployed on a probe card at 5 [sic] GHz? (Ed: answer unclear.)