IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

July 9, 2012

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

October 17, 2011

 

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)

July 26, 2011

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Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:

Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, Read the rest of this entry »


IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

July 12, 2011

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Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are Read the rest of this entry »


Probe Card Cost Drivers from Architecture to Zero Defects

June 17, 2011

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As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.

Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.

Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.

There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.

I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.

 


IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Seven (Tuesday)

June 28, 2010

Here are the highlights from Session Seven – Probe Potpourri of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Boyd Daniels, Texas Instruments, “Very Low Cost Probe Cards – A Two Piece Approach”:

For their “catalog” parts – medium complexity, low volume, and medium number of devices – historically it has been cheaper to blind package (i.e. skip wafer test prior to packaging) and take the yield loss at package test.  The main issue is the high initial cost and maintenance of probe cards is too high relative to the volume of parts to be tested.
Read the rest of this entry »