IEEE Semiconductor Wafer Test Workshop – High Performance Probing – Session Four (Monday)

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Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Bob Davis, Rudolph Technologies, “Testing Probe Cards That Contain Complex Circuitry“:

Over time, probe cards have increased in complexity from simple wire cantilever probes to those including passive components and digital control circuits. Some of these digital control circuits may even contain state based logic. At the same time the physical complexity of probe cards have increased in probe and channel counts, probe density, and total probe force. As a result, state based testing and design-for-test (DFT) processes need to be implemented in a probe card analysis (metrology) environment.

A probe card analyzer (PCA) needs to measure XYZ positions, to measure electrical properties, and to verify the probe wiring of the probes. However, performing these tests are far more challenging due to the complex control circuits. From a verification perspective the problem can be broken in to three pieces: probe head verification, circuit board verification (“classical” board test), and complete assembly verification. The probe head and circuit board verification can be done using existing tools. The challenge remains on how to test the complete assembly with the control logic.

The solution is to define states which determine connections within the probe card. Then one can use standard DFT techniques to improve testability through isolation and controllability. Several examples were shown how to improve test access for different types of state based logic. In addition, state based control allows probe card assembly testing without exposing the control circuit details. This allows intellectual property (IP) of either the probe card vendor or the end customer to be encapsulated and not shared.

Question:

  • Is the probe array shorted (all the way out to the tips) or hanging in space when tested? Main purpose of the PCA is to test electrically all the way through to the probes. Therefore, the probes need to be shorted. But it is also possible to test with the probes not shorted (open).

Dominique Langlois, Altis, “A Smart Probe-Card Data Base, a Key for Success“:

Altis, a former IBM and Infineon joint venture, is a semiconductor foundry venture with the largest independent test capacity in Europe. As such they have an inventory of over three thousand probe cards and probe heads. Not only is each card specific to an end customers device, they have a large mix of probe card technologies, parallelism, and configurations.

To manage this inventory and the operational complexity, they built a real time database to reflect the current status and location of every card. The database permits statistical analysis of the cards since all events (failures and repairs) and true number of touch downs (including retest) are recorded. This information is used to both analyze probe card technology reliability by vendor and to forecast required card inventory.

The test execution software on the test system queries the database and will not allow the operator to use a card that is not approved for production. This has eliminated the inadvertent use of cards flagged with issues. And the database has helped them improve offline cleaning of the probe cards resulting in lower contact resistance once returned to production.

Questions:

  • Was this developed as a commercial database? The program is built on Access but not commercialized. Each fab develops their own tools to help improve their operation and to be more competitive.
  • Does the production system check if the card is released for production? Yes, the test execution system which controls the tester will permit the operator to use a card if it has not been released by an engineer.
  • Is there automatic prioritizing for example to use the worst card? Cards should be equivalent. If there is a worst card, you will have defects.

Erik Jan Marinissen, IMEC Research Institute,Wafer Probing on Fine-Pitch Micro-Bumps for 2.5D- and 3D-SICs

IMEC is developing test methodologies including wafer probe solutions for advanced packaging technology that utilize Through-Silicon Vias (TSVs) to stack semiconductor dies. Examples of TSV construction and micro-bump bonding including good scanning electron microscope (SEM) images illustrate many of the probe challenges. The micro-bumps, some of them as small as 25 µm in diameter and only 5 µm tall on a pitch of 40 µm, are used to form the connection from die to die in a stack. A full wafer of integrated circuits (IC) might contain close to one million micro-bumps.

There are also challenges based upon the type of stacked die package for both 2.5D stacked integrated circuits (SIC) where the dice are placed adjacent to each other (in the same plane) on an interposer and 3D-SIC where the dice are stacked vertically (one on top of another). IMEC has also coined the term “5.5D-SIC” for where there are 3D-SIC stacks next to each other on an interposer (like 2.5D dice).

The main test challenges are:

  • 3D Test Flow – there are many different possible locations for testing in the assembly process. Manufacturers need to determine if the testing will be done pre-bond or post-bond since dice have different accessibility before and after bonding.
  • 3D Test Contents – Since there are new types of defects possible due to the stacking, test patterns will need to detect these new defect types in addition to handling previous test requirements.
  • 3D Test Access – TSVs may create both front side and back side probing issues but it currently is not possible to probe both side of the wafer at the same time. Therefore, careful consideration will need to be used when determining what tests to run at different points in the assembly process.

Today’s probe cards do not meet the requirements of arbitrary probe arrays at 40 µm pitch and smaller for large quantities of micro-bumps. The soon to be issued JEDEC standard for wide I/O dynamic random access memory (DRAM) will have four groups (channels) of 300 TSVs for a total of 1200 TSVs per die in a 6 x 50 grid on 40 µm centers each with a micro-bump.

IMEC has been working with Cascade Microtech to develop a new “Rocking Beam Interposer” (RBI) probe technology that both scales Cascade Microtech’s Pyramid membrane probe technology and improves the performance to address TSV probing. Cascade Microtech now has a probe card that can probe one of the four channels (a group of 300 TSVs) on a wide I/O device for engineering measurements. One of the challenges of the dimensional scale of the micro-bumps is the prober accuracy needs to have better than 1 µm positioning. IMEC is addressing this with Cascade Microtech since they also have a line of high accuracy probers.

IMEC’s goal is to probe a full 3D wide I/O DRAM by the end of year assuming JEDEC finalizes the specification soon.

Questions:

  • How much Z-compression of the probe is necessary to get the force required? The answer is currently not known since IMEC needed to upgrade their prober to work with smaller tips requiring better tip and fiducial registration. They are currently operating in the range of 0 to 100 µm overdrive.
  • When will the probing process be dialed in? IMEC has no experience in developing probe technology so they need to rely on Cascade Microtech to advise. For example, the cleaning media is currently undefined so likely still a matter of months.

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