IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

Semiconductor Wafer Test Workshop (SWTW) Banner

Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are tip burning and current carrying capacity (CCC). Tip burning or melting is damage of just the probe tip due to localized heating. CCC is a reasonable limit for the amount of current that can be passed through a probe. Exceeding the maximum CCC of a probe will cause the entire probe to lose its mechanical strength.

Tip burning / melting is caused by excessive power dissipation at the tip which is primarily a function of the contact resistance (Cres) of the probe to the surface it is contacting. Joule’s first law states that power flowing through a conductor is proportional to the square of the current times the resistance (P = I^2*R) in that conductor. And for a typical probe tip, the Cres dominates the overall resistance since the metal conductivity is high. As the contamination on the tip increases or the tip itself is damaged or worn, the Cres increases to the point where the localized heat destroys the tip. Tip arcing can occur if there is still charge in the power circuitry when the probes touchdown due to improper programming of the tester’s power supply. Severe arcing can destroy the tips quickly while repeated moderate arcing will cause damage to the tips leading to tip burning / melting.

Maximum CCC is a function of probe design and test environment. The probe cross section, length, and material determines the path resistance. The thermal path is determined by the coupling of the probe to the probe head (heat sink). The test environment determines the other thermal conditions (chuck temperature, heat effects from neighboring probes, etc.) and the current.

There are three methods commonly used for measuring CCC:

  1. Current to Failure – The current is increased on a test sample until it is destroyed. (A video was shown of a typical catastrophic failure at a high current level.) This is the standard FormFactor test methodology.
  2. Long Term Stress- A fixed current is applied to a probe that is under load at temperature. The force is then periodically released to simulate touch downs. The probe is observed for changes in droop, discoloration, and spring constant to determine failure point.
  3. ISMI Guidelines – An initial current is applied to a probe for two minutes at room temperature. Then the force is measured. The current is then increased and the procedure repeated to find the point at which the force has dropped to 80% of the original force.

When testing multiple devices under test (DUTs) powered from a common power supply, it is not possible to set per die current limits on the tester. However, if you add circuitry such as FormFactor’s Advanced Tester Resource Enhancement (TRE) you can provide a current trip function to shut off DUTs that draw too much current. This will protect the other devices and permit the testing to continue.

Increasing the number of power probes on a device helps current distribution but current flow isn’t always split evenly between probes. This doesn’t guarantee lower per probe currents but does improve power supply impedance.


  • What temperature does FormFactor do their CCC testing at? Cannot provide a number since the material property is confidential.
  • Have you used thermal paint to verify actual temperatures? Yes, thermal paint has been used. For future experiments a thermal camera may be used for confirmation. You can also verify temperatures by observing the melting point since material properties are known.
  • Can you do TRE current limiters for individual probes? Not on a probe card with 50-60 K probes since at least 10K probes are power probes. And you cannot put 10K power limiters on a very crowded probe card.

January Kister, MicroProbe, “Key Design Parameters to Maximize Probe Current Carrying Capability”:
The International Technology Roadmap for Semiconductors (ITRS) predicts probe pitch decreasing from 130 µm to less than 100 µm by 2016. Thru silicon via (TSV) probing will also require sub-50 µm pitch before 2013. Therefore since the probe diameter needs to shrink to enable tighter pitch between probes, the challenge is how to carry more current through an ever shrinking probe cross-section.

With increasing current densities, CCC of approximately 1 Amp per probe is required for production robustness. Transient currents of over 0.5 A per probe have been observed which may be significantly higher than “steady state” current for some devices.

The variables that determine the CCC of probe include:

  1. Probe Material – bulk, yield, loss of strength at higher temperatures, and probe tip materials
  2. Probe Geometry – resistivity is proportional to the cross section while length determines resistance since resistance is resistivity multiplied by length. Customers prefer long probes to enable additional over drive but short probes have lower resistance resulting in higher CCC. With C4 bumps that have a +/-15% tolerance on height, longer working distance probes are needed but have lower CCC due to long probe length.
  3. Probe Layout – A probe’s CCC is influenced by its neighboring probes. A center probe in 3 x 3 grid has a 15% reduction in CCC due to thermal interactions with the surrounding probes.
  4. Chuck / Wafer Temperature
  5. Probe Tip Contact Resistance
  6. Electrical Duty Cycle – most probes reach steady state in under 2 seconds
  7. Dynamic Cycling – The CCC of a probe may need to be reduced for a larger number of touchdowns due to the stress of the mechanical loading of each touchdown.

In order to optimize the CCC of the power probes, they have build probe heads that combine both regular probes for signals and multi-material (composite) probes for the power and ground probes. These multi-material probes have higher CCC than a standard probe. An example of this type of construction was shown in a scanning electron microscope (SEM) image.


  • In the example of a probe in the center of a 3 x 3 grid, did all 9 probes carry higher current simultaneously or did the outside carry a nominal current? In the evaluation shown, all probes carry the same current.
  • What happens to the inductance & coupling as probe pitch shrinks? If only the only requirement is handling high current then you can use very short probes (i.e. 50 µm like the height of a C4 bump) which provides low inductance. But if you need longer probes due to planarity of the system (bumps, multilayer ceramic planarity, etc.) then the inductance increases.
  • Is final CCC an estimate of all the factors – how do they interrelate? The data presented looked at these factors as independent variables but they do interact.
  • Can you compensate for not enough CCC in the probes by running the prober chuck colder? When the chuck is hot, it does reduce the CCC. So, minus 40 C is an easier condition for CCC in general.

Rainer Gaggl, T.I.P.S. Messtechnik, “Aspects of High Power Probing”:

Examples of high power semiconductor device applications include power switching for renewable energy, electric trains, power grids, electronic power supplies, automotive, and electric vehicles. These devices usually require testing this high power functionality at or above the rated device power level.

For these types of devices, “High Current Probing” (HCP) can be defined as pulses of 1 to 5 A per probe for a few milliseconds. These currents are typically much higher than the current rating of the probes used. Therefore, HCP sometimes results in various probe tip and probe body damage – from minimal to extreme – due to the high currents involved.

Electro-thermal modeling of different configurations including direct current (DC) steady state versus both single pulse and multi-pulse high current shows two regimes of behavior for each probe type studied:
+ Probe tip heating – a region of very fast change in temperature at the tip from the current applied
+ Probe body heating – a region of slow heating and cooling of the probe which is insensitive to current spikes
To enable HCP, a safe operating area region (SOAR) for a probe can be created by combining these regimes to form an operating range that is insensitive to both tip heating and body heating.

To prevent tip burning on a HCP application at STMicroelectronics, a probe card was designed using T.I.P.S.’ MicroClamp current limiters. The MicroClamps are circuits placed in serial with each probe to limit the current flow. Not only did this clamp method eliminate tip burning, a lower variation in RDSON (drain to source resistance in on-state) measurements improved the device yield since the current distribution was more uniform.


  • Any difference in resistance for the power probes? Previous work was presented at SWTW in 2002 on determining different resistance of power probes using a PRVX3 probe card metrology system. It depends on both the specific probe and probe card design.
  • Is the real SOAR much lower than that of the 80% operating region when using ISMI guidelines? Simulation shows a current change of 10% will influence the test results significantly before the 20% force reduction and probe burning seen in the ISMI guidelines.
  • Could this analysis be extended for a more complex probe such as a spring pin with multiple contact points? It may be possible, but you would need to simplify the model to keep it computationally reasonable.

Gert Hohenwarter, GateWave Northern, “Power Delivery Network Analysis – a case for true 3D simulations”:

Power delivery networks (PDNs) need to respond to transients – i.e. be able to deliver power when requested by the device under test (DUT). It takes a long time (in terms of device speed) for a tester to adjust the power suppliers to respond to these transients. Therefore capacitors need to be located in different places along the PDN (in the probe head, probe card, and test system) to smooth out the supply of power. The location and size of the capacitors determines how quickly they can deliver extra power for transients.

The entire power system then needs to be analyzed by modeling and measurement to insure proper performance. An equivalent circuit model will provide acceptable answers for simpler parts of the system. However, you probably need to build a 3D electromagnetic simulation model of the probe card PDN system for greater accuracy.

The models also need to include the on-die PDN circuit whose data is typically unavailable. Using reverse engineering and on die measurement it is possible to obtain equivalent data. A time-domain reflectometer (TDR) measurement permits extraction of capacitance values. While a vector network analyzer (VNA) return loss measurement can determine effective inductance and resistance (at higher frequencies).

Due to the complexity of the overall modeling, the probe card can be split into regions so that 3D modeling of each region can be done separately. The S-parameters can then be extracted for each region and combined in a single SPICE simulation of the entire system. An example showed how a 3D model identified a higher resonance peak which would have been problematic and was not identified when using a simpler 2D model. This difference was due to adding in effects of the printed circuit board (PCB) and bypass capacitors.


  • How to avoid any hidden problem in the PDN? It is best to start with an analysis prior to the design. Of course, the quickest way is to make a measurement on an actual probe card but this is non-trivial and may be too late to change the design of the card to remove problems.
%d bloggers like this: