As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
My event summary recently published inChip Scale Review Tech Monthly:
Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI InternationalTechnology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.
If we were focused on just these two parameters, we could be talking about horses, cars, or airplanes. But throw in density, endurance, and price and it is a horse race of different color. Not only does the winning technology have to balance speed and power, it needs to pack more functionality per area at a lower cost than existing solutions. Along with the endurance to last ten or more years.
Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEESemiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.
Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEESemiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.
Here are the highlights from Session Four – “High Performance Probing” of the 21st annual IEEESemiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEESemiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.
Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:
Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.
As the final presenter at this week’s IEEESemiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
No this isn’t a soliloquy to an Apple iPad that is no longer, but a brief tour of the incredible memory, packaging, and system technology that can be found under the hoods of the original iPad and the iPad 2 along with some of the manufacturing and test implications. These devices clearly demonstrate the new paradigm of “More Than Moore“ where scaling of systems and packaging will propel the next wave of growth in electronics beyond the traditional doubling of performance every two years predicted by Moore’s Law. For many in semiconductor packaging and test engineering communities the issues related to More than Moore have been an academic discussion up to now, but clearly the success of the iPad product line shows the current reality for advanced devices and where the future is headed. Apple and their suppliers took huge risks in developing these new technologies in exchange for substantial returns.
There are so many different types of memory technologies that there is an alphabet soup of acronyms. Ever wonder why we have many different memory technologies some long forgotten with more on the horizon? I refreshed my own memory after last week’s IEEE Nano Technology Council presentation on conductive bridge random access memory (CBRAM).
Here are the highlights from Session Nine – “Productivity / COO” of the 21st annual 
High Technology Business Development - Ira Feldman 