Memory Technology – Off to the Races!

Speed and Power

If we were focused on just these two parameters, we could be talking about horses, cars, or airplanes. But throw in density, endurance, and price and it is a horse race of different color. Not only does the winning technology have to balance speed and power, it needs to pack more functionality per area at a lower cost than existing solutions. Along with the endurance to last ten or more years.

With annual revenues once exceeding $60 B and now running $45 B due to dropping demand and prices, the global market for semiconductor memory is an exciting race. It is hard to believe that NAND Flash has grown to $20 B/year alone since it’s mainstream introduction as removable media only seventeen years ago. With the demand for mobile devices now dominating the electronics market, NAND Flash, which was once the ignored step-sister of the far sexier dynamic random access memory (DRAM), is now gaining all the attention. Most mobile devices have far more non-volatile memory (NVRAM) in the form of NAND Flash than volatile memory such as DRAM in terms of both bits and number of physical semiconductor integrated circuits (ICs) otherwise known as “chips“.  (For a detailed example, see iPad Memories for my description of the memory contained in an iPad.)

So the level of interest at the recent IEEE San Francisco Bay Area Nanotechnology Council’s (SFBA Nano) “Emerging Non-Volatile Memory Technologies” full day symposium shouldn’t have been a surprise. As a member of the SFBA Nano Executive Committee, I knew that we had excellent schedule of world-class speakers. But we were still pleasantly surprised with the final attendance of nearly two hundred which far exceeded our original estimates. As a session chair, I was only one of two speakers that day who did not have a PhD and who was not addressed as either doctor or professor. Even though we had several professors presenting this was not an overly “academic” event since several talked about commercialization work. We also had several extremely distinguished industry researchers including R. Stanley Williams (HP fellow leading the team to develop the memristor) and Stuart Parkin (IBM fellow leading the IBM-Stanford Spintronics research group developing Racetrack and other memory technology) who both presented keynotes.

From lab to fab to killer app?

Yes, all the technologies and approaches presented enable non-volatile storage of information. What differentiates one from the other is how well each performs in the areas of speed, power, functionality and cost. Each needs the right mix of performance for the targeted end application. Both mobile devices and supercomputers need low energy storage and high bit density.

Matthew Marinella from Sandia National Laboratories‘ Advanced Semiconductor Device Research Group discussed the need for memory densities exceeding 1 terabit/cm² per layer and bit switching energies of significantly lower than 1 pJ to enable future generation supercomputers beyond the exaFLOPS systems currently being designed. This is orders of magnitude higher performance in terms of memory density and power consumption than the midterm needs of mobile devices. However, building a supercomputer has substantially higher performance requirements with a budget to match.

As the speed of the computer increases, the main memory size needs to increase along with the speed of the memory (including communications delay time usually expressed as latency), otherwise the processors run out of data and cannot achieve peak performance. Dr. Marinella points out that at the current memory power consumption levels (for both bit storage and communication) it is impractical to build larger memory arrays for next generation supercomputers. (Think requiring one or more nuclear power plants per supercomputer.)  He is marginally optimistic that the recently developed Hybrid Memory Cube will provide sufficient performance to build an exaFLOPS system and believes the higher level of performance described is needed for the future. In particular, they are looking at resistive memory (ReRAM) as a possible path forward since a NVRAM, in general, will consume less power than a DRAM since there is no need for a refresh cycle.

In terms of commercial status, Adesto Technologies is the furthest along with their conductive bridge RAM (CBRAM) according to Michael Kozicki, Professor of Electrical Engineering at Arizona State and Adesto’s Chief Scientist. They are currently shipping a 1 Mbit serial electrically erasable programmable read-only memory (EEPROM) and are building this and other embedded memories with their partner Altis Semiconductor. (I’ve previously written about Adesto’s technology here.)

Yiming Huai, Vice President of Technology at Avalanche Technologies, discussed their 64 Mb magnetoresistive random access memory (MRAM) prototypes built using a 65 nm low power complementary metal-oxide-semiconductor (CMOS) process. Lastly, Dr. Williams disclosed that HP has built memresistors on 300 mm wafers and that their manufacturing partner SK Hynix would be making an announcement later this year.

So which will finish first? It is difficult to say without knowing the race to be run and how these technologies perform in the real world. But it will certainly be exciting to see how these innovative technologies compete for market share.