Memory Alphabet Soup

There are so many different types of memory technologies that there is an alphabet soup of acronyms. Ever wonder why we have many different memory technologies some long forgotten with more on the horizon? I refreshed my own memory after last week’s IEEE Nano Technology Council presentation on conductive bridge random access memory (CBRAM).

The simple answer is big money. This market is propelled by our insatiable demand for more bits. [To skip the technology part of this article and get to the dollars click here.] If you are like most consumers your most pressing question about memory is “which iPad 2?” – 16 GB, 32 GB, or 64 GB? Simply put most people only care about how much the device holds and not about how it holds these bytes or how well it performs. There is plenty of memory magic under the hood of the iPad worth examining.

From a functional perspective, all computer memory can be characterized by:

• Access type – random or sequential
• Persistence – volatile or non-volatile

For a computer to efficiently use memory to run programs (executables) it needs to be true random access memory (RAM) where a single byte (or group of bits) can be retrieved in any order. The most common memory for holding programs is dynamic random access memory (DRAM). Static RAM (SRAM) is an even faster memory structure which is often used to provide a memory cache for DRAM. However, SRAM requires more transistors per bit to build than DRAM therefore it is more expensive. Both DRAM and SRAM are volatile and lose their content when the power is turned off.

Data storage, on the other hand, often requires much larger capacity and is mostly utilized in a sequential or “block” fashion where efficient reading of large quantities is more important than quick random access. It is usually desirable that the data storage has persistence such that it retains the data without consuming power (non-volatile). Like many, I have seen the evolution of non-volatile storage from Hollerith cards and paper punch tape to magnetic tape to floppy disk drives to hard disk drives to most recently NAND flash memory.

As technology develops, the divisions between access and persistence categories have blurred. For example, modern double data rate DRAM (DDR DRAM) uses a wider memory bus (64 bits) and double clocks the data providing data in larger chucks than true random access. This is why a SRAM cache is usually implemented to provide quick access to a particular byte. And memory technology companies are building “combined” memory parts with two types of memory (example: DRAM and NOR flash) in one package to provide a single solution to simplify system architecture. However, the fundamental memory types are still present in this complex packaging solution.

So with all the existing memory technologies, why are there so many companies – both existing memory companies and startups – interested in developing the next new thing?

For starters the memory market is the largest commodity sector of the semiconductor market besides microprocessors. The DRAM market was over $40 B in 2010. The NAND flash market was almost $19 B in 2010 and is expected to grow to $22 B in 2011.

In order to get a slice of these huge markets, new technology needs to compete on the basis of cost and/or performance. Bit density – the number of bits that can be stored in a given area – relates to both cost and performance. The greater the area to fabricate a given memory size the higher the cost (assuming comparable fabrication technology) and the lower the overall storage that can be included in the final product.

Even though Toshiba announced in August (2010) industry leading mass production of 64 Gb NAND flash using 24 nm fabrication technology, the 2009 International Technology Roadmap for Semiconductors (ITRS) placed the present limit of fabrication in the 22 to 16 nm range. If indeed there is a “brick wall” that prevents shrinking the fabrication process further we will soon hit it as the semiconductor industry continues to follow Moore’s Law. Either new fab processes and new materials will be needed or different memory technology will be required to stay on this trajectory. Or both.

The IEEE Nano presentation I attended was “Scalability of CBRAM: Where are we now and how far can we go?” by John Jameson of Adesto Technologies. CBRAM was developed by Adesto’s Chief Scientist Michael Kozicki at Arizona State University. It is also known as a Programmable Metallization Cell (PMC) that changes state by the physical re-location of ions within a solid electrolyte. These ions form a “nanowire” in one state which can be detected by a significant drop in resistance across the cell.

So, why have Adesto’s owners invested over $29 M as reported by VentureBeat? Adesto claims that the fundamental technology can scale down to 12 nm (at least one if not two nodes further than the ITRS’ predictions about NAND flash) at lower cost, higher write speed, and with longer data retention time than flash memory. Short term they are offering to add a “memory layer” to existing CMOS designs and longer term they are positioning themselves to be a “flash killer”. Displacing NAND flash will be a challenge especially since 19.3 billion GB are expected to be sold in 2011 at a remarkably low $1.60 per GB dropping to $0.65 per GB by mid-2012. [Yes, I’ve noticed that Objective-Analysis and iSuppli’s market numbers are not consistent since these would imply a $30B not $22B market in 2011. However, the magnitude is correct and the market is very large.] In addition to today’s dominant suppliers of flash memory (Samsung, Elpida, Toshiba, etc.), some not so small companies such as Infineon Technologies, NEC, and Sony are also working in this area.

If Adesto or others developing alternative memory succeed, there should be a substantial return to their investors which is the cornerstone of venture capital. This is why we have an “alphabet soup” of acronyms for new memory technology.

PS: rounding out this “Alphabet Soup” of acronyms for those craving more technology:

Other alternative non-volatile memory currently available includes ferroelectric RAM (FeRAM) and magnetoresistive RAM (MRAM) . Non-volatile technologies under development include phase-change RAM (PRAM), Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), resistive RAM (RRAM), carbon nanotube Nano-RAM (NRAM), and racetrack memory .

Volatile memory currently under development includes thyristor RAM (T-RAM), zero-capacitor RAM (Z-RAM) , and twin transistor RAM (TTRAM).

For an in-depth discussion of many of these new memory types, the ITRS published a summary of “Assessment of the Potential & Maturity of Selected Emerging Research Memory Technologies Workshop & ERD/ERM Working Group Meeting (April 6-7, 2010)“.