Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.
Testing the Supply Chain
Much the same as the world, test is not simply black or white but varying shades of grey and a jumble of colors. Test has continually responded to semiconductor technology challenges to provide the right solutions. As a result, the organizational placement and “supply chains” for test have rarely been Continue reading “Coupling & Crosstalk: Testing the Supply Chain”
For the last fifteen years the International Technology Roadmap for Semiconductors (ITRS) has been looking fifteen years into the future. Based upon technology requirements and other inputs, ranging from the gate size of transistors to advanced packaging technology, the Test and Test Equipment Technical Working Group (Test TWG) has worked to develop the requirements for test technology and equipment.
The Test TWG is over seventy volunteers with deep technical expertise in test from around the world and from every sized company – Fortune 100 to individual consultants – and every type of company – semiconductor independent device manufacturer (IDM), fabless semiconductor, foundry, outsourced assembly and test (OSAT), automated test equipment (ATE) suppliers, prober, probe card, socket, handler, and more. Through Continue reading “IEEE Semiconductor Wafer Test Workshop 2014 Presentation”
Wow! The Burn-in and Test Strategy (BiTS) Workshop just turned 15! The world of semiconductors has certainly changed over the years. And the BiTS Workshop has kept up with what is “Now & Next” in the burn-in and test of packaged integrated circuits (ICs). These achievements were celebrated in style by the more than three hundred participants at the recently held 2014 BiTS Workshop in Mesa, Arizona.
Integrated circuits using 2.5D advanced packaging are shipping. 3D packaging with thru-silicon vias (TSV) has been demonstrated. “5.5D” packages may not be far behind. Probe card suppliers have made progress building interconnect technology for the micro-bump arrays. Standards committees have started defining IC interface standards and test access protocols.
But what does the Test Engineer and Management really want? What can they afford? What are the most likely scenarios? Factors that determine which test technology can support the desired test flow are examined. In particular, probe card technology for probing TSV bumps and potential usage models are reviewed.
As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:
Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.
Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:
Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).
As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”
Tommie Berry (FormFactor, Inc.), “Actual vs. Programmed Over Travel for Advanced Probe Cards”:
As the number of probes on a probe card increase, the total force required to compress these probes – know as probe force – is increasing. With high force the actual over travel (AOT) – also know as overdrive – of the probe is often significantly different than the programmed over travel (POT) programmed in the prober. Even though memory test engineers with very high probe count cards have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)”
The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.
Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.
Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:
Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.
Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:
Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.
One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.
As the final presenter at this week’s IEEESemiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.
Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.
There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.
I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.
Even though this sounds like the start of a Carnac the Magnificent comedy act, these are some of the answers from my Probe Card Market model. I keep my model current so I know both industry and company specific performance as well as to make predictions. You don’t have a model? Are you reacting instead of predicting?
I usually try to ignore items that are unattributed, however a recent blog posting in the ElectroIQ blog “How To Fix FORM” caught my attention. It is true that FormFactor’s current difficulties are being discussed widely. However, the simplistic analysis and suggestions of this unknown “industry insider” need a reality check. The writer gets some of the overall problems right but may be missing the boat on the solutions.
Here are the supposed anonymous industry insider’s suggested fixes:
The wildly varying projections for the semiconductor market in general and the wafer probe market in specific makes me believe that many analysts are simply torn between reporting their tea leaf readings and the scores on their dartboard. A hopefully more reliable source is VLSI Research and their annual probe market survey is eagerly anticipated every spring. One may argue about methodology but on the whole they do an excellent job of painting a comprehensive picture.
Their optimistic forecast is heartening but increased sales volume doesn’t always translate into profits and downturns when they occur can be fatal. Do you prepare for growth like a hare or a tortoise? Do you build excess capacity (“Field of Dreams“), take and fulfill new orders with lots of overtime and temporary workers, or do you forgo new business that bears high incremental start-up costs?
Ellis Huang, MPI Corporation, “Novel Vertical Probe Card Solution for Multi-DUTs and RF Device on 3 GHz Applications”:
This project was done with UMC using MPI’s VPC vertical probe technology to test Bluetooth modules at 2.45 GHz.
In order to provide a 50 ohm signal as close to the device under test (DUT) as possible, they added dummy ground pins to the probe head around critical signal pins. Even though these signal pins already had adjacent ground pads that were probed on the device, these dummy pins (probes) were positioned closer to the signal pin thereby maintaining the 50 ohm impedance. The dummy pins are connected to other grounds via the copper flex circuit on the space transformer. Continue reading “IEEE Semiconductor Wafer Test Workshop – Challenges of RF Probing – Session Nine (Wednesday)”
Jay Thomas, Grund Technical Solutions, LLC., “Probe Cards with Modular Integrated Switching Matrices”:
For the last 30 years, most scribeline parametric testing has been approximately 85% Current-Voltage (I-V) testing and 15% Capacitance-Voltage (C-V) testing. For these types of tests a 10 MHz bandwidth switch matrix has been sufficient.
However, some of the larger fabs such as HP, IBM, and Intel have started performing pulsed Current-Voltage (PIV) and electrostatic discharge (ESD) testing. These customers started this type of testing about four years ago unknown to Agilent & Keithley (the two largest DC parametric tester suppliers). This PIV and ESD testing requires high frequency switch matrices with 1 GHz bandwidth. [For more about ESD testing please see Jay’s second presentation below in this session.] Continue reading “IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)”
Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:
For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk. However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS). Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin. Continue reading “IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)”
Mark McLaren, Integrated Technology Corporation, “Metrology Solutions for Very Large Probe Cards”:
Over the past few years as the number of memory devices to be tested in parallel has increased so has the size of probe cards to support this multisite testing. A few years ago memory probe cards grew to 440 mm diameter and recently they increased to 480 mm diameter. Now a similar growth in size has been seen for non-memory applications. Even though the parallelism (number of devices to be tested at once) has increased (but not on the scale of memory parallelism), the size increases have been the result of pushing more testing from package test to wafer test. These additional tests have required more local test resources (circuitry close to the device being tested) which require more real estate on probe cards. Continue reading “IEEE Semiconductor Wafer Test Workshop – Standards and Methods – Session Four (Monday)”
The 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) started this evening. Rumor has it that attendance is over 240 this year which is a vast improvement over last year’s 160 or so attendees. At the peak the conference had almost hit 600. Things started off well with a reception where I had the chance to catch up with many industry friends and colleagues.
Balancing test coverage versus test cost. What does a test failure mean? Value of yield increase
… and how it impacts your bottom line!
A poorly implemented semiconductor test cell may pass integrated circuit (IC) parts that are either defective or have marginal performance. They can cause the electronic devices in which they will be assembled to either malfunction or completely fail. However, two other conditions require evaluation. Having false negative test “escapes” is expensive in terms of final product test failures, warranty costs, customer dissatisfaction, etc. In turn, the false positive test escapes needs to be balanced against the cost of false negative failures where otherwise good parts fail the tests and are discarded. Test engineers, product managers, quality engineers, and operational managers needs to make either implicit or explicit decisions as to the proper balance in adjusting the test limits. The goal is to cost effectively approach “zero defects” without “throwing out the baby with the bath water”.
A test process generally categorizes the item or device being tested as “pass” or “fail”. Sometimes passing devices are graded (typically by speed or other desired quality) and failing devices are often grouped by failure mode. “Coverage” is how well a particular test process measures the functionality and specifications of a given device. If every feature and specification is tested then it is said to have 100% test coverage. However, exhaustive testing is usually expensive due to long test times which translates in to operational costs including the depreciation of the test system and greater test setup complexity (equipment and development cost). Sometimes complete coverage is not possible or practical so there needs to be a trade-off between coverage and cost.