Tag: Printed Circuit Boards (PCB)

Riding Off Into the Sunset – BiTS 2013

Sunset over Phoenix, Arizona during BiTS Workshop
Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Continue reading “Riding Off Into the Sunset – BiTS 2013”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

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Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”