As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?
This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of content, engagement, and environment. Once again, the weather was fantastic even for those of us from milder climates: sunny and warm 70-80 F during the day. The Hilton pulls out all of the stops for this conference with a great facility and darn-tasty vittles. The weather and hotel merge to form the foundation of the great environment. It is no wonder why BiTS keeps returning to this particular “ranch” every March. And many attendees are repeat participants.
But the real cornerstones of the event are the technical conference and the expo. Having been roped-in to join the committee, I quickly learned of all the hard work that goes into getting the right content. My ten gallon hat is off to the other committee members for wrangling their technical sessions. Over the years, the committee has done an amazing job expanding the horizons of this conference from “just” sockets for test and burn-in into all of the “tooling” (load boards, fixturing, thermal management, cabling, and yes even some probe cards) required for testing semiconductors.
I had the pleasure of wrangling Session 6 “And, at the Wafer Level” which addressed the challenges of performing final test and burn-in at the wafer-level. As the deployment of wafer level chip-scale packaging (WLCSP) increases, many users have adopted or investigated the use of spring-pin based wafer probe cards for final test. Jim Brandes (Multitest) in “Spring Probes and Probe Cards for Wafer-Level Test” and James Migliaccio (RF Micro Devices) in “A Comparison of Probe Solutions For an RF WLCSP Product” covered this topic well. Steve Steps (Aehr Test Systems) discussed many of the issues that drive the need for wafer-level burn-in in “Wafer-Level Burn-in Decision Factors”. In “Bridging Between 3D and 3D TSV Stacking Technologies”, Belgacem Haba (Invensas) described new technology to increase the performance of multiple stacked dynamic random access memories (DRAM) in one package and package-on-package (PoP) applications. Invensas’ Dual Face Down (DFD), Quad Face Down (QFD), and Bond Via Array (BVA) technologies should help to fill the product roadmap gaps between existing solutions and true 3D packaging which is not expected to be widely available sooner than 2016. Mr. Haba was awarded the “Most Inspirational” presentation. Once again, I would like to thank all of the presenters, especially those in my session, for their hard work.
There wasn’t any hog-calling or yodeling on the Talking Points panel hosted by Françoise von Trapp (Queen of 3D, Impress Labs). It was my pleasure to join Scott Jewler (Advanced Nanotechnology Solutions), Chris Scanlan (Deca Technologies), and Sitaram Arkalgud (Invensas) to discuss “Interconnectology: Inspiring a Paradigm Shift”. As Dennard Scaling, which has been the main engine allowing the semiconductor industry to keep up with Moore’s Law, may be coming to an end and the price per transistor is no longer dropping there is a need for More than Moore solutions. Interconnectology is the development of new interconnect technologies – at the integrated circuit (IC) package, printed circuit board (PCB), and system level – to enable new or improved performance at lower overall product cost. Take a look at Françoise’s write-up about the panel and keynote by Bill McClean (IC Insights) for additional insights into Interconnectology. And feel free to add your comments below on your thoughts of adding Interconnectology to the lexicon.
The expo had a vast array of exhibitors from various parts of the test supply chain. From starting material (plastics, ceramics, and high performance alloys) to interconnect elements (spring pins, elastomers, PCBs, cables, etc.) to capital equipment (burn-in environmental systems, packaged part handlers, etc.). There were services companies, system integrators, and custom solution providers. All of the exhibitors were focused semiconductor test and the electrical, thermal, and mechanical solutions required to provide the interconnect from the device under test (DUT) to the test system. The expo is a very popular component of the workshop as it provides the opportunity to find solutions for one’s test challenges and to see the latest developments. And maintaing a focus on test keeps it from becoming overwhelming unlike the much larger expos which try to have something for everyone. From the comments I heard, everyone always enjoys the one-on-one engagement and networking opportunities the expo provides. It is no wonder that the expo sold out (again) and a secondary ballroom was added to accommodate everyone who wanted to exhibit.
The BiTS Workshop is an enjoyable and worthwhile event if you are involved in test due to the excellent content and networking. It is extremely valuable to understand the test technology challenges and appropriate test solutions. And we certainly have a bit of fun along the way. So as we hit the trails to tackle our technology challenges, I look forward to crossing paths soon. If I can ride shotgun and help you out partner, don’t hesitate to holler!