Coupling & Crosstalk: Trust your Paranoia!

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2019 edition on pages 11-12.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Trust Your Paranoia!

President Ronald Reagan’s use of the Russian proverb “Doveryai, no proveryai” was the perfect soundbite to describe the 1987 Intermediate-Range Nuclear Forces Treaty. What does this and Andy Grove’s “only the paranoid survive” have to do with semiconductors? Continue reading “Coupling & Crosstalk: Trust your Paranoia!”

Coupling & Crosstalk: KGD Redux?

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Fall 2019 edition on pages 9-10.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

KGD Redux?

Known Good Die (KGD) – Is this a case of “everything old is new again” or acid reflux from a mature semiconductor industry? Today there is a greater need than ever to know that a given semiconductor die is good before proceeding to package it. This particular quest for the holy grail has provided plenty of Continue reading “Coupling & Crosstalk: KGD Redux?”

Coupling & Crosstalk: Testing the Supply Chain

change canstockphoto28381385_focalpoint_c350x350 Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2018 edition on pages 8-9.

Testing the Supply Chain

Much the same as the world, test is not simply black or white but varying shades of grey and a jumble of colors. Test has continually responded to semiconductor technology challenges to provide the right solutions. As a result, the organizational placement and “supply chains” for test have rarely been Continue reading “Coupling & Crosstalk: Testing the Supply Chain”

Chip Scale Review: The Three Most Important Words for 3D ICs?

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Continue reading “Chip Scale Review: The Three Most Important Words for 3D ICs?”

Coupling & Crosstalk: Name Calling

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2013 edition on pages 13-14.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Name Calling

What’s in a name? A lot! A name itself might not mean much but it can trigger expectations and stereotypes. In the United States we have red states and blue states depending on which political party has the majority vote. Similarly, when someone labels themselves on the basis of their political party affiliation (Republican, Democrat, Libertarian, Independent, etc.) others Continue reading “Coupling & Crosstalk: Name Calling”

Riding Off Into the Sunset – BiTS 2013

Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Continue reading “Riding Off Into the Sunset – BiTS 2013”

SEMI ISS: Sense of Scale

Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013

Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.

The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers ~~needing~~ wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.

The whiplash comes from Continue reading “SEMI ISS: Sense of Scale”

Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span Continue reading “Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging”

MEMS Testing and Reliability 2012 – Session 3

Can reliability and production testing keep pace with the explosive growth in microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren’t really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of Continue reading “MEMS Testing and Reliability 2012 – Session 3”

MEMS Testing and Reliability 2012 – Session 2

Session 2

Mårten Vrånes (Director of Consulting Services, MEMS Journal) in “A Test-centric Approach to MEMS ASIC Development” discussed alternatives to the traditional co-design of the MEMS element and application specific integrated circuit (ASIC). As many MEMS devices require an ASIC to control and/or sense the MEMS element the most logical approach is to design both parts in parallel. However the scope of such a development effort is often beyond the resources – both in terms of talent and funding – for many companies especially startups.

Mr. Vrånes started with the challenges and pitfalls of ASIC development for MEMS devices. There are challenges regardless of Continue reading “MEMS Testing and Reliability 2012 – Session 2”

MEMS Testing and Reliability 2012 – Session 1

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960’s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960’s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include Continue reading “MEMS Testing and Reliability 2012 – Session 1”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

Road-to-450-mm-Semiconductor-Wafers-Ira-Feldman-SWTW-2012.png — Click image to download presentation

Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)

Semiconductor wafer test workshop swtw sign

Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:

Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]

Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)

Semiconductor wafer test workshop swtw sign

Here are the highlights from Session Two “Optimizing Probe Depth Performance” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Tommie Berry (FormFactor, Inc.), “Actual vs. Programmed Over Travel for Advanced Probe Cards”:

As the number of probes on a probe card increase, the total force required to compress these probes – know as probe force – is increasing. With high force the actual over travel (AOT) – also know as overdrive – of the probe is often significantly different than the programmed over travel (POT) programmed in the prober. Even though memory test engineers with very high probe count cards have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons: Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

Thinking Big: $1 Trillion MEMS Market – Part 2

Part 1 described Janusz Bryzek‘s ambitious goal of a $1 trillion market for microelectromechanical systems (MEMS) that was the focus of the MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium. In addition, sensor swarms, road mapping and market numbers were covered. Challenges, example applications, and key takeaways are discussed here along with a final score card on the $1 T market.

Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 2”

Thinking Big: $1 Trillion MEMS Market – Part 1

Usual business advice includes thinking big to win big. Some organizations create Big Hairy Audacious Goals. Others like to find new markets that are underserved and grow to be number one. The semiconductor industry has Moore’s Law – the premise that the minimum cost point is achieved by doubling the number of transistors per chip every two years – driving it forward for almost fifty years.

Janusz Bryzek set a dramatic and ambitious goal of $1 trillion sales for the microelectromechanical systems (MEMS) market in 2022. Even though the MEMS market is expected to have “only” $12 billion in revenue in 2012, he isn’t being called a fool. Having cofounded eight seminal Silicon Valley MEMS companies and currently the Vice President of MEMS Development at Fairchild Semiconductor (which recently acquired his last company), Janusz is taken quite seriously.

Yes, at last week’s MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium there were some who Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 1”

Silicon Valley Test Workshop – 2nd Year “Rocks”

2 5D? 3D? What? 3D IC Packaging - Ira Feldman — Click image to download presentation

Back for the second year (with a minor name change), the Silicon Valley Test Workshop is an unpolished gem. Looking past the rough edges (minor logistical issues), what really shines through is the interaction of the participants. This conference really has Continue reading “Silicon Valley Test Workshop – 2nd Year “Rocks””

Semiconductor Packaging: 2.5D, 3D, and Beyond!

MEPTEC's 2.5D, 3D and Beyond Packaging Conference

The MEPTEC “2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.

Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with Continue reading “Semiconductor Packaging: 2.5D, 3D, and Beyond!”