Coupling & Crosstalk: Testing the Supply Chain

change canstockphoto28381385_focalpoint_c350x350 Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2018 edition on pages 8-9.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Testing the Supply Chain

Much the same as the world, test is not simply black or white but varying shades of grey and a jumble of colors. Test has continually responded to semiconductor technology challenges to provide the right solutions. As a result, the organizational placement and “supply chains” for test have rarely been Continue reading “Coupling & Crosstalk: Testing the Supply Chain”

Chip Scale Review: The Three Most Important Words for 3D ICs?

Source: Bryan Black (AMD)
Source: Bryan Black (AMD)

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Cost! Cost! Cost! are the three most important words for 3D semiconductors.

Just like the real estate mantra “location, location, location”, if you don’t have a solution to the cost issues nothing else matters for 2.5/3D integrated circuit (IC) integration and packaging. It is true that, Xilinx is shipping “production” quantities of 2.5D parts and others have sampled 3D parts. However, there are plenty of technical challenges yet to be solved to make 2.5/3D practical in volume production at reasonable cost and yield.

Every presenter at the 3D Architectures for Semiconductor Integration and Packaging symposium and conference stressed cost as a major concern, requirement, or feature. Over the ten years the discussion at this conference, organized by RTI International Technology Venture Forum, has moved from Continue reading “Chip Scale Review: The Three Most Important Words for 3D ICs?”

Coupling & Crosstalk: Name Calling

good bad dice canstockphoto9654181 250x320Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Summer 2013 edition on pages 13-14.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Name Calling

What’s in a name? A lot! A name itself might not mean much but it can trigger expectations and stereotypes. In the United States we have red states and blue states depending on which political party has the majority vote. Similarly, when someone labels themselves on the basis of their political party affiliation (Republican, Democrat, Libertarian, Independent, etc.) others Continue reading “Coupling & Crosstalk: Name Calling”

Riding Off Into the Sunset – BiTS 2013

Sunset over Phoenix, Arizona during BiTS Workshop
Sunset over Phoenix, Arizona during BiTS Workshop

As the Burn-in & Test Strategies (BiTS) Workshop 2013 fades into the sunset (queue the music), here is a round-up of the highlights. There were gun fights in the corral as well as technical questions for the presenters. The saloon girls and gunfighters took an edge off of the “geek” factor. This year over three hundred fifty people come to the “Circle BiTS Ranch” (aka the Hilton in Mesa, Arizona) for the premier conference focused on what is new and next for semiconductor test tooling and strategy. Oh, did I mention that the theme this year was Western?

This was the 14th annual BiTS Workshop, which has achieved the perfect conference trifecta of Continue reading “Riding Off Into the Sunset – BiTS 2013”

SEMI ISS: Sense of Scale

Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013
Intel shows first fully patterned 450 mm semiconductor wafer at SEMI ISS 2013

Attending the SEMI Industry Strategy Symposium (ISS) is like drinking from a fire hose with the additional risk of whiplash. Don’t get me wrong, it is an exquisite fire hose but sometimes the data presented can be overwhelming at this conference of semiconductor supply chain executives. The majority of the attendees and presenters are executives from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. And the executives present from the semiconductor manufacturers are typically the “end customers”.

The greatest value of SEMI ISS, beyond the networking, is the strategic overview of the entire semiconductor ecosystem. What are the market drivers, the technology needed, and the roadmap status of this industry? It is true that we all know where we need to head courtesy of Moore’s Law and the International Technology Roadmap for Semiconductors which attempts to keep us on that trajectory. The pressure of consumers needing wanting greater functionality at lower costs is relentless. Much of the technological detail of this ecosystem is addressed in a myriad of other forums throughout the year. ISS ties these technical requirements, development needs, and business needs back to the strategic direction and desires of the global marketplace.

The whiplash comes from  Continue reading “SEMI ISS: Sense of Scale”

Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging

Lego Blocks (flickr: antpaniagua)
Lego Blocks (flickr: antpaniagua)

My event summary recently published in Chip Scale Review Tech Monthly:

Is 3D semiconductor packaging really the Lego of the integrated circuit (IC) world? It is a great analogy for the range of possible solutions and flexibility provided by different flavors of 3D packaging (2.5D on interposer, 3D, 5.5D, etc.) and “colors” (homogenous and heterogeneous) of die stacks. Plenty of pictures of Legos and scanning electron microscope (SEM) images were shown last week at the RTI International Technology Venture Forum symposium and conference “3-D Architectures for Semiconductor Integration and Packaging”. Presenters clearly articulated the great promise of what could be built with 3D packaging. At the same time, progress towards solving the multitude of challenges to make this technology as pervasive, if not as easy to use and fun, as Legos was discussed.

The challenges span Continue reading “Chip Scale Review: News from 3-D Architectures for Semiconductor Integration and Packaging”

MEMS Testing and Reliability 2012 – Session 3

Can reliability and production testing keep pace with the explosive growth in  microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

 

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren’t really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of Continue reading “MEMS Testing and Reliability 2012 – Session 3”