Semiconductor Packaging: 2.5D, 3D, and Beyond!

MEPTEC's 2.5D, 3D and Beyond Packaging Conference

The MEPTEC2.5D, 3D and Beyond – Bringing 3D Integration to Packaging Mainstream” conference was a mixed-bag. Yes, it is always exciting to hear about new suppliers and progress. But it is disconcerting to realize that the price of progress is an ongoing burden on our industry’s supply chain.

Subramanian Iyer (IBM) and Theresa Sze (Oracle) started with excellent overviews of why 3D semiconductor packaging solutions are needed to solve memory bandwidth and latency challenges to continue improving microprocessor performance. They both recognized that there are many challenges in implementing these new packaging solutions including power, thermal, and economic issues. Theresa also demonstrated why high speed optical interconnect is not be practical for multiple data channels since a single transceiver module was a significant portion of the die area and provided only 1/20 of the desired bandwidth. Phil Marcoux (ALLVIA) continued with a description of different interconnect methods and substrates that could be used to form different 2.5D and 3D configuration solutions. During a discussion of what a large die was, Dr. Iyer quipped that some IBM engineers would like to use an entire wafer for one die (which reminds me of Seymour Cray‘s early work). He went on to say they consider anything over 40 mm on a side a large die.

The outsourced assembly and test (OSAT) companies then provided updates on their assembly process technology. Marnie Mattei (Amkor Technology) provided a timeline of when they think the different kinds of chip stacking using thru-silicon vias (TSV) will be in production. Tom Strothmann (STATS ChipPAC) had a similar table of timing and end applications. Amkor currently has 40 µm pitch micro-bumps qualified for production. They are working to have 30 µm ready in the first quarter of 2012 at which time they will start 20 µm development. Marnie did say Amkor is not seeing the demand for 20 µm pitch as early as they original expected. In my opinion, anything that allows test technology an opportunity to catch up to the packaging technology is a good thing since it appears that test (once again) is lagging behind packaging development. As far as I know, there is not a production proven test solutions to contact these bumps at 40 µm pitch let alone tighter pitches.

Marnie, Tom, and Muster Wang (ASE Group) all reviewed the many variations in process flows and their companies’ silicon interposer work. All three companies noted they would take wafers with the vias formed (but prior to the wafer thinning and exposing of the vias) or the fully thinned wafers (with all the TSV processing completed). The OSATs did appear to have a preference though – for handling and yield reasons – to do the wafer thinning and finish the processing in their facility. Needless to say that both the end customer and foundry may prefer to do it the other way by sending only thinned wafers. Therefore, the OSATS say they will support both models.

Dr. Choon-Heung Lee (Amkor Technology) provided the keynote address in which he reviewed Amkor’s silicon interposer and 3D packaging technology. He also made the point more than once, with specific price data, that the technology had to fit within their customer’s cost budget regardless of the performance. A major concern is both the number of process steps and the different capital equipment required to do the wafer thinning and the micro-bump interconnect since both the process cost (number of steps) and capital equipment utilization contribute significantly to the cost of the packaging. In reviewing the technical challenges he did identify that TSV testing is a big issue but he would “leave it for another” forum or group to address starting with the Known Good Die conference to follow. Once again, the packaging and test communities did not develop this technology collaboratively and it is not clear that are they have yet fully engaged to solve the issues together.

Supply chain and back side integration challenges were addressed by Sunil Patel (GLOBALFOUNDRIES), Herb Reiter (eda2asic Consulting), and Rich Rice (ASE Group). Sunil discussed the different business models: Foundry Plus where the foundry is responsible for everything including test and assembly, OSAT Plus where the OSAT take responsibility for thinning the wafers, finishing the interconnect and any damage that may occur, and a Third Party model where an independent party owns putting all the pieces together including the memory subsystem. Herb reviewed the need for open standards to enable the entire ecosystem to enable 3D packaging along with some of the status of the groups working on these standards. Lastly, Rich reviewed some of the concerns in the supply chain starting with the $400 B gap in capital investment between the wafer fab equipment (“front end”) and assembly & test (“back end”). He also reviews some examples where the current technology may provide lower cost solutions than 3D packaging. These existing solutions may continue to be more attractive in price until the volume demand grows to fully utilize the equipment required. Therefore, careful consideration is required before switching to a new technology just because it is new especially if the performance of these solutions are not yet required.

Aveek Sarkar (Apache Design) presented some of the multi-physics challenges of power and thermal simulation of stacked die packages. He also compared simulations based upon using full die layouts (circuit based schematic) of all the dies in the stack (“concurrent simulation”) versus replacing some of the die with predictive models. The models allow simulation without disclosing the complete details (i.e. the intellectual property) of a die that may be provided by another vendor. In the two examples shown the results from each method correlated well with the other. Thermal modeling of different 2.5 and 3D packages were shown by Zeki Celik (LSI). Placing dies side by side on a silicon interposer (i.e. the 2.5D configuration) provided the best thermal performance. When the die are stacked with an interposer between them the two die reach the same temperature and the bottom die adds to the heat of the top die. The worst configuration studied is a stack without an interposer where the memory die is on top of the logic die (i.e the most common 3D configuration discussed): both die reach the same temperature which is even higher than previous example since the thermal path to the logic die is insufficient to allow the heat to escape. Nozad Karim (Amkor Technology) reviewed signal integrity modeling on 2.5D and 3D stacked packages. Key to these simulations is accurately determining the equivalent capacitance of the TSV. Due to the complexity of the system, traditional package simulation is challenging. In addition, thermal and mechanical variations will change the electrical characteristics requiring a multi physics approach for accuracy. Therefore both new tools and methodologies are needed to do this analysis.

The conference closed with a presentation by Rick Ried (STATS ChipPAC) providing an overview and “teaser” about the Known Good Die conference to follow.

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