MEMS – High Technology Business Development

Coupling & Crosstalk: A Trillion Sensors?

Janusz Bryzek's TSensor Vision — Janusz Bryzek’s TSensor Vision

Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Winter 2014 edition on pages 10-11.

Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column by mixing technology and general observations is thought provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Name Calling

Whatever you desire “there’s an app for that!” Dream big or small, it is very likely a software program is already available. But what if you dream in hardware? Hewlett-Packard is building applications with one MILLION sensors. Robert Bosch is dreaming of 1,000 sensors per person, i.e. seven TRILLION. Janusz Bryzek is aiming for one TRILLION per year.

Standardized smartphone hardware platforms and application “stores” have significantly lowered the cost and time to develop and sell applications. One might argue Continue reading “Coupling & Crosstalk: A Trillion Sensors?”

Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!

Below is my event summary recently published in Chip Scale Review Tech Monthly:

Market adoption is increasing rapidly for wafer level packaging (WLP) as it is applied to a greater range of applications. The shift of “Post-PC” from desktop to mobile devices has driven the development of WLP into the mainstream by providing extremely space efficient and low cost packaging. There has and will continue to be many technical and business challenges in packaging devices on wafer (or other substrate) en masse instead of on an individual basis.

Similar to wafer level packaging technology itself, the 2013 International Wafer-Level Packaging Conference (IWLPC) Continue reading “Chip Scale Review: International Wafer Level Packaging Conference (IWLPC) Turns 10!”

Coupling & Crosstalk: Measuring Up

bathroom scale Coupling & Crosstalk is my column in the MEPTEC Report. This column appears in the Spring 2013 edition on page 14-15.

Measuring Up

Tap to turn on. Wait for it to zero. Step on. I haven’t lost any weight, still 205 pounds even with all this exercise and careful eating? Step off, step back on. 212 pounds. Damn, wrong answer. Step off, step back on. 206 pounds. Okay maybe the first reading was right. Optimistically record 205 pounds. Does this nightly dance sound familiar? Not only are bathroom scales the bearer of bad news, their Continue reading “Coupling & Crosstalk: Measuring Up”

MEMS Testing and Reliability 2012 – Session 4

Can reliability and production testing keep pace with the explosive growth in microelectromechanical system (MEMS) based product volumes? Soon it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. In order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability. This was the focus of the MEMS Testing and Reliability 2012 conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 4

Mervi Paulasto-Kröckel (Professor, Aalto University) in “On the Reliability Characterization of MEMS Devices” examined the current methods for reliability assessment in MEMS devices and identified necessary improvements. Currently, the reliability of MEMS devices are evaluated in the functioning state. A sensor is tested by applying a known stimulus and comparing the sensor output while varying the test conditions such as temperature, humidity, etc. MEMS actuators are similarly tested by providing a known input and measuring the output of the actuator over the range of test conditions. Significant deviation between the expected and measured result indicates a failure. Simple functional test is appropriate for manufacturing quality testing however it is inadequate for measuring and improving device reliability.

Professor Paulasto-Kröckel compared these processes commonly used to estimate MEMS reliability to those used in the microelectronics industry. She identified major methodology changes required Continue reading “MEMS Testing and Reliability 2012 – Session 4”

MEMS Testing and Reliability 2012 – Session 3

Session 3

Pavan Gupta (Vice President of Operations, SiTime) provided a cautionary tale in “Packaging and Reliability Qualification of MEMS Resonator Devices”. Historically many MEMS companies have failed to start the device and package co-design as early as possible even though packaging was upwards of 80% of the product cost. [Perhaps they aren’t really using a concurrent engineering methodology?] Even though the cost of packaging has dropped significantly, the complexities and risks related to packaging remain high.

There are many challenges related to MEMS packaging since without a reliable and qualified package, it is not possible for one’s customers to easily and confidently integrate a MEMS product into their end product. In SiTime’s case they had a double challenge of Continue reading “MEMS Testing and Reliability 2012 – Session 3”

MEMS Testing and Reliability 2012 – Session 2

Session 2

Mårten Vrånes (Director of Consulting Services, MEMS Journal) in “A Test-centric Approach to MEMS ASIC Development” discussed alternatives to the traditional co-design of the MEMS element and application specific integrated circuit (ASIC). As many MEMS devices require an ASIC to control and/or sense the MEMS element the most logical approach is to design both parts in parallel. However the scope of such a development effort is often beyond the resources – both in terms of talent and funding – for many companies especially startups.

Mr. Vrånes started with the challenges and pitfalls of ASIC development for MEMS devices. There are challenges regardless of Continue reading “MEMS Testing and Reliability 2012 – Session 2”

MEMS Testing and Reliability 2012 – Session 1

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960’s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960’s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include Continue reading “MEMS Testing and Reliability 2012 – Session 1”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)

Semiconductor wafer test workshop swtw sign

Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:

Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]

Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)”

Thinking Big: $1 Trillion MEMS Market – Part 2

Part 1 described Janusz Bryzek‘s ambitious goal of a $1 trillion market for microelectromechanical systems (MEMS) that was the focus of the MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium. In addition, sensor swarms, road mapping and market numbers were covered. Challenges, example applications, and key takeaways are discussed here along with a final score card on the $1 T market.

Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 2”

Thinking Big: $1 Trillion MEMS Market – Part 1

Usual business advice includes thinking big to win big. Some organizations create Big Hairy Audacious Goals. Others like to find new markets that are underserved and grow to be number one. The semiconductor industry has Moore’s Law – the premise that the minimum cost point is achieved by doubling the number of transistors per chip every two years – driving it forward for almost fifty years.

Janusz Bryzek set a dramatic and ambitious goal of $1 trillion sales for the microelectromechanical systems (MEMS) market in 2022. Even though the MEMS market is expected to have “only” $12 billion in revenue in 2012, he isn’t being called a fool. Having cofounded eight seminal Silicon Valley MEMS companies and currently the Vice President of MEMS Development at Fairchild Semiconductor (which recently acquired his last company), Janusz is taken quite seriously.

Yes, at last week’s MicroElectronics Packaging and Test Council (MEPTEC) 10th annual MEMS Technology Symposium there were some who Continue reading “Thinking Big: $1 Trillion MEMS Market – Part 1”

Two Conferences – Two Industries Challenged By Post PC Era

Apple_iPad_Intro_March_2011_Tim_Cook_172M — Tim Cook introducing Apple's latest iPad

The “Post Personal Computer” (Post PC) era became the hot topic when Tim Cook introduced the latest iPad last week. Yes, calling it a “revolution” is definitely hype that is part of Apple‘s Post PC marketing campaign. Hype aside, it is clear that there has been a marked shift in digital hardware for the consumption of content and communication. The PC – be it a Windows, Mac, or Linux based system – is no longer “the device”. It is now one of many devices including portable music players (dominated by iPods), smart phones (lead by iPhones and Android based systems), and tablets (dominated by iPads). The shift is large and the impact is huge. To understand how big, watch the first three minutes of Mr. Cook’s presentation. Then you will understand why Apple had the largest market capitalization of any US company in February – the numbers are staggering.

Even though many were surprised to learn that we are now “Post PC”, some of us who have been developing strategies for the electronic supply chain have Continue reading “Two Conferences – Two Industries Challenged By Post PC Era”

Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers

The MEMS Testing and Reliability 3rd Annual Conference gets high marks: excellent speakers focused on an emerging topic and it was large enough to have “critical mass” while allowing everyone to interact. It was well produced by MEMS Investor Journal and MEPTEC.

My presentation, “Semiconductor Wafer Test Technology and Trends: Lessons for MEMS Test Engineers“, covered the differences between testing semiconductors and microelectromechanical systems (MEMS). I reviewed the progress in test technology over the last fifty plus years, from simple cantilever probe cards to large full wafer contact probe cards, developed to reduce the cost of test.

I discussed lower cost solutions that appear counter-intuitive since they require increased technical and operational complexity. Challenges of testing MEMS devices while still on wafer (prior to packaging and singulation) were discussed along with a review of MEMS solutions at this year’s IEEE Semiconductor Wafer Test Workshop.

With the proper skills, experience, and perspective it is possible to avoid “re-inventing the wheel” and to develop the best strategy to profitably introduce new technologies to high volume manufacturing.

IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”

IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)

Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:

Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.

One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.

Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)”

IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)

On Sunday evening June 12th, 2011 Jerry Broz, the general conference chair, opened the IEEE Semiconductor Wafer Test Workshop welcoming us to the 21st year with a combined total attendance of over 5,000. He also briefly highlighted the positives in recent market trend data from the Semiconductor Industry Association (SIA) and VLSIresearch.

Dr. William Chen, Senior Technical Advisor, ASE Group, provided the keynote presentation “Backend to the Front Line”:

Dr. Chen started with Continue reading “IEEE Semiconductor Wafer Test Workshop – Opening Session & Keynote (Sunday)”

MEMS Technology Summit – Day One – AM (2)

CardioMEMS_s2_sensor — CardioMEMS EndoSure Wireless Pressure Sensor

From the MEMS Technology Summit at Stanford University, here are the highlights from the second morning session on Tuesday October 19, 2010:

Professor Thomas Kenny, Stanford University, Keynote: “MEMS Goes Mainstream, but Where are We Going?”

What are we trying to do? Make money – others will cover that topic – and to enable capabilities. But we need to look at how well we have achieved this.
Nanotechnology promises are un-fulfilled: There has been lots of hype and promises in the literature for over ten years. But what we are missing is the “technology” side of Nanotechnology. Perhaps Nanotechnology is an oxymoron? Continue reading “MEMS Technology Summit – Day One – AM (2)”

MEMS Technology Summit – Day One – AM (1) – Special Presentations

Yole Product Tornado - SEMICON West — MEMS Products Phases of Development - Yole Research

Last Tuesday,the MEMS Technology Summit at Stanford University, opened with a welcome by Professor Roger Howe. Roger not only provided a brief history of MEMS at Stanford, he was his characteristic gracious self and welcomed even those with close ties to Berkeley especially the Berkeley Sensor and Actuator Center (BSAC). Truth-be-told even though Roger is a Mudder first, Continue reading

WOW! MEMS Technology Summit

Having just completed a very busy two and half days at the MEMS Technology Summit at Stanford University, my lasting impression is “WOW”! The conference really did live up to their theme “Lessons from the Past and Vision for the Future”.

From the pre-conference tour of the Linac Coherent Light Source at SLAC National Accelerator Lab to the presentations by the best and brightest in the MEMS industry to the closing reception this evening, there was no end to information, interaction and networking, all of the highest quality. As part of the theme, the conference celebrated Continue reading “WOW! MEMS Technology Summit”