MEMS Testing and Reliability 2012 – Session 1

It was my pleasure to attend the MEMS Testing and Reliability 2012 conference to see the considerable progress made in these areas as microelectromechanical system (MEMS) based product volumes accelerate. We may soon get to the point where it will be the rare consumer product that does not include a MEMS device bringing us closer to the possibility of a $1 trillion MEMS market. But in order to achieve greater adoption of the technology, cost and quality goals will need to be met through testing and reliability, the focus of this conference produced by MEMS Journal and MicroElectronics Packaging and Test Council (MEPTEC).

Session 1

Mario Correa (MEMS Test Engineering Manager of Fairchild Semiconductor) started with “Evolution of MEMS Test Solutions” reviewing how test equipment and processes have evolved from the 1960’s to today. There have been major changes to test methods developed for non-MEMS sensors first used with military and aerospace MEMS sensors in the late 1960’s where the annual volume was measured in thousands of units to those used today for over three billion units shipped yearly to the consumer electronics market. It has been a challenge keeping up with the high triple digit growth rates from 2009 to 2012 including gyroscopes +189%, microphones +347%, and digital compasses +778%. MEMS accelerometers grew “only” +78% during this period. (Growth data per Yole)

These changes include the evolution of the test system from a purpose built single device tester to modular high parallelism multisite testers. As the parallelism increased, the number of required stimuli also increased. Older testers for an accelerometer or gyroscope originally only tested one axis a time which was fine since these devices only measured one axis. As three axes sensors become the norm, three axes testers had to be developed to avoid having to test these parts three times, once for each axis. And now that six axes devices – three gyroscope axes plus three accelerometer axes – are extremely common with even greater axes devices (some have nine with the addition of magnetic sensors) on the way, test system complexity has grown to accommodate these needs.

As the system complexity has increased, so has the speed of these systems growing from less than 100 units per hour (UPH) in the late 1990’s to upwards of 7,500 to 10,000 UPH today. While the total capital cost of these systems has increased by an order of magnitude, the effective cost per UPH per axis has dropped by two orders of magnitude from $2,700 to $30.

Since many of these test systems operate on devices in their final packaged form, there has been an increased demand to test the MEMS elements while still on wafer to avoid the cost of packaging a bad device. Many MEMS sensors also include a fairly costly application specific integrated circuit (ASIC) increasing the need to know that the MEMS and the ASIC are both good before connecting them together and encapsulating in the final package. Since most MEMS elements are singulated and attached individually to either the ASIC die or to a common substrate, bad MEMS elements or bad ASIC die can be skipped and removed from the process flow. 

For inertial sensors that can be electrostatically actuated, or for those to which a test structure can be added to move the sensor electrostatically, dynamic wafer testing has been developed. Dynamic wafer test applies an electrical stimulus pulse to move the sensing elements and then measures the resulting movement of the sensor as it resonates and decays. Even though this stimulus is not the same as the device will see in final test or actual usage, the response “signature” can be correlated to “good” and “bad” parts. Companies that offer technology to test the MEMS elements while still on wafer prior to electronic integration and packaging include Solidus Technologies and SPEA.

Lastly, there is an increasing trend from device specific test equipment towards a generalized test cell approach similar to those used in final (semiconductor) package test. Different companies such as Focus Test, SPEA, Multitest, and Teradyne offer part “handlers” that move individual parts to groups of parts (in tray or strip with as many as 72 or 144 sites tested in parallel), stimulus units, and testers that can be combined and reconfigured to test a wide range of products.

 

In “Applying the CMOS Test Flow to MEMS Manufacturing”, Mike Daneman (Manger of MEMS Operations, InvenSense) described the different approach InvenSense has taken to test the almost 100 million parts a year they ship.

With their unique Nasiri-Fabrication (NF) process the MEMS device wafer is directly attached to the ASIC wafer using wafer bonding to become the package. Like other processes, the ASIC wafer is fabricated and wafer tested as usual with typically high yields. On the MEMS device wafer they only measure a small set of parameters during test, without the need to stimulate the sensor, to determine if the quality level is acceptable to use. Extensive testing of each MEMS device is not warranted prior to wafer bond since they have to use the entire wafer with no provision to discard bad MEMS elements. Fortunately, they have improved the yield of their devices to the level at which direct wafer to wafer bonding makes economic sense.

After the wafers are bonded together, the combined ASIC and MEMS dies are singulated and encapsulated in the final package. For final test they use custom-built test systems designed for high throughput by mechanically stimulating and testing a large number of parts in parallel. Surprisingly, these systems have a bowl-feeder which are often used for very high volume low-cost parts but aren’t often used on such high value parts which typically require traceability. InvenSense achieves the needed traceability back to the die locations on the original ASIC and MEMS wafers through individual serial numbers programmed into each ASIC during wafer test. They use special test and calibration routines designed into the ASIC to improve the efficiency of the test process and to lower test cost. The ASIC can also measure test structures on the MEMS device to further optimize the test process and device performance. Traceability through the entire process from ASIC wafer and MEMS wafer to final part allowed them to quickly improve their yields to further reduce costs.

By integrating both the design of their device and manufacture processes for ASIC and MEMS alike – which are often designed separately and fabricated without consideration to the other parts – InvenSense was able to make tradeoffs between each element to provide greater overall efficiency and lower cost. This allows them to successfully ship such large quantities of parts and to make their process available to others to develop innovative MEMS devices.


Stay tuned for additional summaries of MEMS Testing and Reliability 2012 to be posted shortly.

3 Responses to MEMS Testing and Reliability 2012 – Session 1

  1. Ivan Puchades says:

    Thanks for the update Ira. Looking forward to your review of the next sessions.

  2. David Powers says:

    Very interesting series Ira, I thoroughly enjoy it.

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