IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)

Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:

Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.

One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.

In addition to the Cratering Test, they take a smaller sample of probed pads and use a focused ion beam (FIB) to cross section the layers that compose the bond pad and those below it. Examining these side images will show crack formation that may not be visible in the Cratering Test.

They did a design of experiments (DOE) to determine which parameters caused crack formation in their traditional pad structure of four metal layers interconnected by tungsten (W) vias. They discovered that high probe overdrive (OD) and high number of touch downs combined with short probe tips made the most damage especially under the “heel” of the probe tip.

They next examined how different pad structures correlated to cracking. The traditional structure was the weakest while a structure of a simple aluminum pad with no lower metal layers or vias was the strongest. However, a metal pad with no interconnect is not useful since it is impossible to route a signal to it. They did discover that as the metal density of the interconnect layers below a pad are reduced so is the rate of cracking. In addition, mesh patterns or slotting can limit the propagation of the cracks in these lower metal layers.

They conclude that you need to prevent the silicon dioxide (SiO2) from “bending” when the pad is probed since it is stiffer than the aluminum metal. Using copper (Cu) pads with low K dielectrics the reverse is true since the copper is stronger than the dielectric. They are continuing to study this to determine if it is acceptable to bend the copper pads.

Questions:

  • If 100 µm OD is harsh – what is normal? 1 to 2 mil (25.4 to 50.8 µm) OD for cantilever probes is normal. Short probe tips and 6 touch downs are also extreme.
  • Tip shape and planarity is hard to control as the probe wears. What tip diameter was used? 0.8 mil tip diameter.
  • What was the hardness of pad metal? Not yet known. They plan to use nanoindentation to compare Al pads to Cu pads.
  • How about vertical probes? The scrubbing of a cantilever probe allows stress to be released. Vertical probing with shorter scrubs may be applying extra stress to the structure below and increase the fracture rate.

Mike Slessor, MicroProbe, “Flexible Vertical MEMs Probe Card Technology for Pre-Bump and eWLP Applications”:

As discussed in Dr. Chen’s keynote address, Embedded Wafer Level Packaging (eWLP) is a new type of wafer level chip scale packaging (WLCSP). One or more die are embedded in a molded carrier that is larger than the area of the die or dice. A signal redistribution layer (RDL), typically copper traces, is then added to fan out the die connections to a larger pitch that is compatible with the system printed circuit board (PCB). Lastly solder balls or bumps are applied at the larger pitch for use in attaching to the system PCB. Some of these balls may be over the molded carrier without any silicon beneath them.

Most flip chip packaging is probed after the device has had the solder balls or bumps attached. I.e. the probe contacts the solder bump not a flat metal bond pad. However, since it desirable to only use known good die (KGD) when building a wafer of eWLP parts the need to probe the pad prior to solder bump attach has re-emerged. Currently pad pitches for this pre-bump testing is in the range of 130 to 180 µm but it is quickly transitioning to less than 100 µm. Probing full grid at 100 µm pitch requires vertical probe technology. Other challenges of this probing include pad openings shifting from 50 µm octagonal towards 40 µm and the need for low force since the pads are placed over circuits.

He presented results from three different customer qualifications of pre-bump probing using MicroProbe’s Mx (MEMS probes):

  • Customer A required low force probing since their pads are over active circuits. They achieved 2 to 3 gF at 65 um OD using the Mx probes. Good results included scrub marks that were short (8 to 15 µm), maximum scrub depth after 8 TDs of 0.55 µm, and no ILD cracking found with 60 µm OD.
  • Customer B die had smaller pads (55 µm) than normal on a 180 µm pitch array containing 7,500 pads. They achieved overall planarity of < 24 µm and scrub mark placement that was 13 µm of center.
  • Customer C performed a scrub depth experiment which determined the maximum scrub depth to be 0.56 µm after 6 touchdowns.

From these qualification results, Mx technology enables probe before assembly for eWLP parts and can also be used before bumping for flip chip parts if desired (permitting data collection prior to bumping).

Question:

  • If they are probing KGD to form reconstituted wafers, how do they test the reconstituted wafers? Some customers are not testing after the wafer is reconstituted / processed as eWLP. If the RDL has a large pitch they could test as a standard WLP if they can’t live with a nominal fall out after completing the processing of the eWLP.

Amy Leong, MicroProbe, “Evaluation of New Probe Technology on SnAg and Copper Bumps”:

[Amy presented on behalf of the primary author Alexander Wittig of GLOBALFOUNDRIES who was unable to attend.]

GLOBALFOUNDRIES tested MicroProbe’s Mx product to determine which of two different probes (Mx-150a and Mx-150b – each with a different tip design and metallurgy) worked best for two package types. The package types were copper (Cu) pillars and tin-silver (SnAg) bumps.

In order to perform accelerated life testing, small test probe cards were built with only 22 probes each (a Mx probe can support over 20,000 probes). Using shorted wafers containing either bumps or pillars at a 150 µm pitch, this test probe card required 60,000 touch downs per wafer.

They examined scrub marks and characterized contact resistance at varying current for the different configurations. The Mx-150a had superior performance on Cu pillars while the Mx-150b performed better on the SnAg bumps.

In addition, since the Mx probes require lower force for stable contact (approximately 3.5 gF/probe at 19 µm OD) versus a Cobra-style vertical (typically 10 gF/probe at 53 µm OD) this technology allows larger probe arrays on existing wafer probe systems. This avoids the need to upgrade “thousands” of probers to handle the force requirements of higher probe counts. They plan to do additional characterization work on the force requirements of high probe count probe cards.

Questions:

  • Why did different tip designs make a big difference in electrical characterizations? They haven’t done mechanical characterizations or studies of the oxides, etc. However, they believe most of difference is due to fretting interactions.
  • With the size of the flat / rectangular tip of the Mx-150b was there sliding off the apex of bump? No, they didn’t see sliding off the bump.

One Response to IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)

  1. […] Hunter’s presentation is a follow-on from last year’s presentation where they use both low force cantilever probes with small tips and high force cantilevers to […]

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