Tag: IEEE

IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

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Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)

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Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:

Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.

BE Precision Technology took a different approach by Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 8 (Wednesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)

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Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:

Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).

The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 7 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)

Here are the highlights from Session Six “Meet the Challenge” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Robert Stampahar (SV Probe ‐ An Ellipsiz Company) and Wally Haley (Qualcomm), “Meeting the 1st Silicon: An Alternate Approach for Reducing Probe Card Cycles”:

Unlike other devices which can be tested in packaged form using a test socket, wafer level chip scale packages (WLCSP) rely completely on wafer probe cards for test. A load board with a test socket can usually be designed and fabricated quickly enough that the bring up and debug of new silicon designs is not delayed. When using a wafer probe card that contains a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer, the delivery of the probe card is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 6 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)

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Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.

Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:

Awarded Best Overall Presentation

As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 5 (Tuesday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)

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Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE 
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:

Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 4 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)

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Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:

Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]

Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 3 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)

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Here are the highlights from Session Two “Optimizing Probe Depth Performance” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Tommie Berry (FormFactor, Inc.), “Actual vs. Programmed Over Travel for Advanced Probe Cards”:

As the number of probes on a probe card increase, the total force required to compress these probes – know as probe force – is increasing. With high force the actual over travel (AOT) – also know as overdrive – of the probe is often significantly different than the programmed over travel (POT) programmed in the prober. Even though memory test engineers with very high probe count cards have Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Session 2 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)

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Here are the highlights from the Welcome and Session One “Process Improvements for HVM” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.

Jerry Broz (SWTW general conference chair) started with several sets of numbers: SWTW attendance (up), semiconductor revenue and wafer statistics (problems). and probe card market (up). The problem with semiconductor statistics are  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Welcome & Session 1 (Monday)”

IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)

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This year’s IEEE Semiconductor Wafer Test Workshop started on Sunday June 10th with a pleasant surprise. Due to a welcomed but unexpected wave of seventy walk-in registrations, there was insufficient seating at the opening dinner. Thankfully the hotel staff quickly adjusted to accommodate these additional guests. Attendance and interest in this year’s workshop was clearly up.

Jerry Broz, general conference chair, welcomed everyone with a brief overview and presented prizes for the first annual golf tournament. We then quickly proceeded with business as Matt Nowak (Senior Director, Advanced Technology, Qualcomm CDMA Technologies) provided the keynote “Emerging High Density 3D Through Silicon Stacking (TSS) – What’s Next?” Mr. Nowak discussed the increased amount of hype within the 3D semiconductor packaging market in the last year with everyone announcing something. And Thru Silicon Vias (TSVs) technology has already been in high volume production for image sensors for several years now but at a significantly lower density than for 3D packaging.

Why the great interest recently in 3D packaging using TSVs today? Three simple reasons:  Continue reading “IEEE Semiconductor Wafer Test Workshop 2012 – Opening Session & Keynote (Sunday)”

Green on the Industrial Scale

Molecular Layer Deposition of Polymers – George, Yoon & Dameron [4]

Many exotic materials or materials with special properties are processed using extreme temperature and pressure often with toxic starting materials. In semiconductors, molecular beam epitaxy (MBE) to build single crystal structures and sputtering are common methods of physical deposition to deposit thin films. Both are done using a very high vacuum. MBE heats the atomic materials until they sublimate and land on the desired surface. Sputtering uses a gas plasma to knock a few atoms of material off a “target” and onto the desired surface. There are also different chemical deposition processes including electroplating which uses metal salts dissolved in a solution bath, chemical vapor deposition (CVD) which uses high vacuum, and atomic layer deposition (ALD) which is similar to CVD but uses two half-reactions of gas phase precursors. 

Limitations imposed by extreme temperature, extreme pressure, and toxic materials combined with a typically slow deposition rate make it is difficult to economically run these processes on an industrial scale for high volume manufacturing. But what if there was a process that  Continue reading “Green on the Industrial Scale”

Memory Technology – Off to the Races!

Speed and Power

If we were focused on just these two parameters, we could be talking about horses, cars, or airplanes. But throw in density, endurance, and price and it is a horse race of different color. Not only does the winning technology have to balance speed and power, it needs to pack more functionality per area at a lower cost than existing solutions. Along with the endurance to last ten or more years.

With annual revenues once exceeding $60 B and now running $45 B due to dropping demand and prices, the global market for semiconductor memory is an exciting race. It is hard to believe that NAND Flash has grown to Continue reading “Memory Technology – Off to the Races!”

IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)

 

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Nine – “Productivity / COO” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Doron Avidar, Micron, “Ghosting – Touchdown Reduction Using Alternate Site Sharing“:

Even though memory testers can support very high parallelism, with smaller memories (in terms of capacity and dimensions) there are more die per wafer requiring Continue reading “IEEE Semiconductor Wafer Test Workshop – Productivity / COO – Session Nine (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)

Semiconductor Wafer Test Workshop SWTW bannerHere are the highlights from Session Eight – “RF Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 15, 2011.

Seenew Lai, MPI, “High Bandwidth (>2.5 Gbps) and Fine Pitch (< 30 µm) Cantilever Probe Card“:

The data rate of liquid crystal display (LCD) drivers are increasing to the point that traditional cantilever probe cards cannot support the required bandwidth. Using electromagnetic simulation it was determined Continue reading “IEEE Semiconductor Wafer Test Workshop – RF Probing – Session Eight (Wednesday)”

IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)

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Here are the highlights from Session Seven – “High Temp / Extreme Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Kevin Fredriksen, SPA GmbH, ”MSO – Multi-Site Optimizer”:

Most wafer probers do not supply intelligent stepping algorithms to calculate the most efficient sequence of moving the wafer relative to the probe card. (Ed: At the core of this is a traveling salesman problem.) The situation is exacerbated when Continue reading “IEEE Semiconductor Wafer Test Workshop – High Temp / Extreme Probing – Session Seven (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)

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Here are the highlights from Session Six – “Probe Potpourri” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Marc Knox, IBM, “The Development of a Flexible and Efficient Chip Thermal Imaging Capability“:

Traditional burn-in systems hold multiple printed circuit boards (PCBs) with one or more devices in burn-in sockets to provide temporary electrical interconnect to a device under test (DUT). These PCBs and sockets are known as “burn-in boards”. And the systems in which they are loaded are “ovens” that permit temperature stressing, sometimes at both hot and cold temperatures, while stimuli are supplied to the chip. The purpose of “burning-in” a device is to screen for infant mortality in an accelerated manner.

The IBM team adapted a burn-in board system to Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Potpourri – Session Six (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Spring Pin Probing – Session Five (Tuesday)

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Here are the highlights from Session Five – “Spring Pin Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 14, 2011.

Brandon Mair, Texas Instruments, “WSP-Wafer Socket Probe for Flip Chip Applications“:

Wafer socket probe (WSP) technology has demonstrated better physical and electrical performance and lower cost of ownership (COO) than traditional vertical probe cards for testing wafer level chip scale packages (WLCSP) at 0.4 mm (400 µm) pitch. These WSP probe heads are typically built Continue reading “IEEE Semiconductor Wafer Test Workshop – Spring Pin Probing – Session Five (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)

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Here are the highlights from Session Three – “Power Probing” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Michael Huebner, FormFactor, “A Hot Topic: Current Carrying Capacity, Tip Melting and Arcing”:

Power consumption per dynamic random-access memory (DRAM) is increasing to as high as 400 mA or more under normal test conditions. At the same time the number of DRAMs being tested in parallel – and sharing the same power supply – is increasing. Therefore, the risk of current damage to probes is increasing.

Two distinct, but related concerns are Continue reading “IEEE Semiconductor Wafer Test Workshop – Power Probing – Session Three (Monday)”

IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use Continue reading “IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)”

IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)

Here are the highlights from Session One – “Probe Challenges” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Stevan Hunter, ON Semiconductor, “Use of Harsh Wafer Probing to Evaluate Various Bond Pad Structures”:

Recent product needs such as bond [pads] over active circuitry (BOAC), the use of copper (Cu) wire bonding, increased wafer probe touch downs (as many as 6 TDs), and the desire for greater device reliability has driven the need for more robust bond pads to survive wafer probing.

One method for checking for damage to the device from the probing process is via the “Cratering Test”. They etch off the top aluminum (Al) metallization layer of the pad to visually inspect for damage in the underlying titanium-nickel (TiN) barrier metal layer. If there is a problem they can spot a “crater” in the metal. They continue etching to remove the TiN layer to look for additional damage in the layer(s) below.

Continue reading “IEEE Semiconductor Wafer Test Workshop – Probe Challenges – Session One (Monday)”

Probe Card Cost Drivers from Architecture to Zero Defects

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As the final presenter at this week’s IEEE Semiconductor Wafer Test Workshop (SWTW), I outlined how critical it is to understand the true cost of a product’s architecture in “Probe Card Cost Drivers from Architecture to Zero Defects“. Without a proper understanding of these costs – especially for fully custom high technology products such as wafer test probe cards – it is impossible to maintain a sufficient gross margin. Gross margin is essential to maintain the health of a company and to fund the research & development required for innovation.

Many companies in the semiconductor test market have entered a period that Steve Newberry identified in his 2008 speech “Semiconductor Industry Trends: The Era of Profitless Prosperity?” that parallels the aluminum industry in the 1970’s. And without the means to fund innovation, companies have no future especially when faced with the double threat of Moore’s Law – increasingly harder technical requirements delivered at lower cost.

Yes, there were a few in the audience who appeared pleased since they are confident that their products are on the right path. There were others who may have been upset based upon their company’s direction. I would argue that a proper diagnosis – regardless of how disturbing – is essential to drive the proper cure.

There is plenty of opportunity in the test market and reasons for optimism. The key to long term prosperity is to really understand the fundamentals of the business and not be blinded by the technology.

I thank those who stayed for the entire conference and welcome your thoughts below. And I will be posting more about the conference (including my summaries) in the next few weeks.

 

IEEE Nanotechnology Symposium 2011 – Keynote

Dr. Narayan
The IEEE San Francisco Bay Area Nanotechnology Council held their 7th annual symposium this week. As in the past, the council presents an excellent program. This year’s program focused was “Nanotechnology – Consumer Applications.”

Here are my notes from the keynote presentation by Dr. Spike Narayan, Functional Manager IBM, “Nanotechnology: Leveraging Semiconductor Technologies to Address Global Challenges.”

He asks: can we leverage semiconductor technology to address global challenges of environment, energy, healthcare, and water? Others have made a compelling argument that Continue reading “IEEE Nanotechnology Symposium 2011 – Keynote”

SolFocus: Focused on System Economics

At Tuesday’s IEEE Nanotechnology Forum, Phil Metz, Director of Business Development for SolFocus, discussed their technology in his presentation “SolFocus Concentrator Photovoltaics – An Introduction“. Though I enjoyed learning about their concentrator photovoltaic (CPV) technology (the presentation was appropriately focused for the audience), I had a greater appreciation for their integrated system approach including the economics. This was evident in the non-technical details he shared. As an early adopter with a residential photovoltaic (PV) system, I was surprised when comparing systems beyond the core technology.

Both CPV and PV systems convert the energy radiated from the sun to direct current (DC) power. Most “grid tie” systems then use an inverter to convert the DC power to alternating current (AC) power which is then fed into the power grid. Beyond these basic similarities, there are large differences in technology, complexity, and economics between the systems.

Continue reading “SolFocus: Focused on System Economics”

IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)

Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.

Gert Hohenwarter, GateWave Northern, Inc., “Hidden Performance Limiters in the Signal Path”:

For high frequency signals, designers typically pay attention to avoiding coupling to adjacent signal lines to prevent cross talk.  However, they need to look at many other areas of the design including coupling to power or sense lines, signal impedance mismatch, resonances, and the power distribution/delivery system (PDS).  Coupling and mismatch may lead to resonances which reduce the operating speed or reduce the switching margin. These areas may also increase crosstalk increasing noise levels and also reducing switching margin. In addition, problems in the PDS may also reduce operating speed or switching margin.
Continue reading “IEEE Semiconductor Wafer Test Workshop – Signal Integrity – Session Five (Tuesday)”

IEEE Semiconductor Wafer Test Workshop – Opening Session (Sunday)

The 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) started this evening. Rumor has it that attendance is over 240 this year which is a vast improvement over last year’s 160 or so attendees. At the peak the conference had almost hit 600. Things started off well with a reception where I had the chance to catch up with many industry friends and colleagues.

After dinner, Jerry Broz the General Chair kicked things off with the “Probe Year in Review”. In summary:
Continue reading “IEEE Semiconductor Wafer Test Workshop – Opening Session (Sunday)”

IEEE Consumer Electronics Society – Conductive Inkjet Technology

Last night I attended the IEEE Santa Clara Valley Consumer Electronics Society monthly meeting. The main presentation was by Joel Yocom, Business Development Manager for Conductive Inkjet Technology Ltd.

His presentation will be posted here later.

Joel presented an overview of inkjet technology and how they are applying it to printing circuits. They have developed a process that allows them to inkjet a catalytic ink which after UV curing allows the electroless (e-less) plating of copper. Given the choice of inkjet systems from scanning formats where the print head moves to fixed heads where the material moves past the head they have a wide range of potential substrate sizes and formats to choose depending on the end application. Continue reading “IEEE Consumer Electronics Society – Conductive Inkjet Technology”

IEEE Nanotechnology Symposium – Session 7 – Nano-Enabled Energy II


Here are the highlights from Session 7 – Nano-Enabled Energy II from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Dr. David Predergast, Lawrence Berkeley National Laboratory (LBNL) Molecular Foundry, “Nature of Nano-Scale Interfaces and Mechanisms for Solar Energy Conversion.”

IEEE Nanotechnology Symposium – Session 6 – Nano-Electronics


Here are the highlights from Session 6 – Nano-Electronics from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Vijendra Sahi, VP Corporate Development and GM of the QD Soleil division, Nanosys, Inc.

“From Concept to Creation: The Journey from R&D to Everyday Products.”

IEEE Nanotechnology Symposium – Day Two – Plenary


Here are the highlights from the Plenary session on day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Dr. Burton Lee, Stanford University, “State of European Nanotech.”

IEEE Nanotechnology Symposium – Session 5 – Nano-Processes


Here are the highlights from Session 5 – Nano-Processes from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Note: I will post the the link for the slides once it becomes available.

Dr. Hans Stork, VP and CTO Applied Materials, “Nanotechnology in Semiconductor Industry.”

IEEE Nanotechnology Symposium – Session 4 – Nano Materials

Here are the highlights from Session 4 – Nano Materials from day two of the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Eric Granstrom, General Manager and V.P. of R&D, Cima NanoTech – “Self Aligning Nano Technology for Electronics.”

  • First product Self Aligning Nano Technology for Transparent Electronics (SANTE) is transparent conductive film produced by self aligning silver nanoparticles.
  • For the same transparency, it has 1/10 the resistance of Indium Tin Oxide (ITO).  Also doesn’t yellow shift the color.
  • Based upon current consumption, it is projected that there is only a 7 year supply of ITO.  China controls 80% of this supply.
  • Largest initial market is displays which have one or more (LCDs have two) conductive films.

    • Continue reading “IEEE Nanotechnology Symposium – Session 4 – Nano Materials”

IEEE Nanotechnology Symposium – Day One (Sessions 1 – 3)

Here are today’s highlights from the IEEE San Francisco Bay Area Nanotechnology Council 6th Annual Symposium“Nanotechnology: State of the Art & Applications”

Presentation archive for talks not linked below. Updated as the council receives the presentations.

Dr. Michael Liehr, VP Strategy CNSE Albany, “State of US Nanotech.”

  • College of Nanoscale Science and Engineering (CSNE).  Not organized around traditional degrees (ME, EE, Chem-E, etc.) but around nanoscience, nanoengineering, nanobioscience, & nanofinance.
  • Due to R&D increasing as a percentage of revenue, very few companies will be able to continue making the investments in process development on their own.  Therefore, over time there will be a migration to 2 or 3 technology clusters (or “camps”) worldwide.

    • Continue reading “IEEE Nanotechnology Symposium – Day One (Sessions 1 – 3)”

Richard Elkus – Winner Take All

US is losing its competitiveness due to financial issues and off-shoring of production.

Tonight I attended an excellent presentation by Richard Elkus, Jr. at the IEEE Components, Packaging, and Manufacturing Technology Society (CPMT) Santa Clara Valley Chapter monthly meeting. He spoke about how the United States is losing its global competitiveness due to our financial issues and our inability to manufacture technology domestically.

Early in his career at Ampex he did the product planning for and led the team that introduced the VCR. In 1970, they partnered with Toshiba to manufacturer the units. He then illustrated with multiple examples,  how we lost our ability to innovate and to remain competitive when we “off shored” the production of a given technology. This is also the subject of his book Winner Take All: How Competitiveness Shapes the Fate of Nations.

IEEE 125th Anniversary Celebration

Computer History Museum by Dzou @ wikipedia.org
You can always learn something by hearing top notch presenters speak both in terms of content and style. And even after traveling the world, you may find hidden gems in your own backyard…

This evening I attended a local celebration for IEEE‘s 125th Anniversary. This was structured as a reception (code word: “networking”) followed by several keynote speeches.

First up on the program was a presentation to SRI (formerly known as the Stanford Research Institute) to recognize the 40th anniversary of the first transmission on the the ARPANET (the predecessor of the internet). At that time there were just four nodes: SRI, UCLA, UC Santa Barbara and University of Utah. A large number of the original engineers were on hand to have their achievement recognized.
Continue reading “IEEE 125th Anniversary Celebration”