July 16, 2012
Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.
Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:
In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is Read the rest of this entry »
July 9, 2012
Here are the highlights from Session Eight “Probe Process and Metrology” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.
Rob Marcelis (BE Precision Technology ‐ The Netherlands), “H3D Profiler for Contact Less Probe‐Card Inspection”:
Probe cards require inspection since they are consumables subject to wear. Changes in probe position or shape can damage the semiconductor devices they are testing. As probe cards increase in size and probe count, the probe cards themselves are becoming more expensive to test in terms of test time and complexity. Each new test system typically requires an expensive “motherboard” for the probe card metrology tool to simulate the mechanics of the tester and provide electrical interconnect to the card for electrical testing.
BE Precision Technology took a different approach by Read the rest of this entry »
July 5, 2012
Here are the highlights from Session Seven “Fine Pitch Probing Challenges” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.
Jose Horas (Intel Mobile Communications ‐ Germany), “28nm Mobile SoC Copper Pillar Probing Study”:
Intel Mobile Communications (IMC, previously Infineon Wireless) has started to switch from tin-silver (SnAg) solder bumps to copper pillars (CuP) with SnAg caps for attaching their die to packages. Since the bumps and pillars are formed on the wafer prior to testing of the devices the wafer probe process must accommodate both. CuP offer several advantages over SnAg bumps: tighter pitch (now at 120 µm and able to scale smaller versus 150 µm for SnAg bumps), lower substrate costs due to relaxed design rules, and lower assembly costs (easier to under fill).
The MicroProbe Apollo (vertical buckling beam) probe cards optimized for low force probing using 2.5 mil diameter probes were Read the rest of this entry »
July 3, 2012
Here are the highlights from Session Six “Meet the Challenge” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.
Robert Stampahar (SV Probe ‐ An Ellipsiz Company) and Wally Haley (Qualcomm), “Meeting the 1st Silicon: An Alternate Approach for Reducing Probe Card Cycles”:
Unlike other devices which can be tested in packaged form using a test socket, wafer level chip scale packages (WLCSP) rely completely on wafer probe cards for test. A load board with a test socket can usually be designed and fabricated quickly enough that the bring up and debug of new silicon designs is not delayed. When using a wafer probe card that contains a multilayer ceramic (MLC) or multilayer organic (MLO) space transformer, the delivery of the probe card is Read the rest of this entry »
July 2, 2012
Here are the highlights from Session Five “New Probe Card and Contact Technologies” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 12, 2012.
Tsutomu Shoji (Japan Electronics Materials Corp. ‐ Japan) and Takashi Naito (Advantest ‐ Japan), “Full Wafer Contact Breakthrough with Ultra‐High Pin Count”:
Awarded Best Overall Presentation
As the number of probes on probe cards increase due to greater parallelism, driven by the desire for one touchdown testing and the future transition to 450 mm wafers, the total force required to probe a wafer increases if there is no reduction in the force per probe. This wafer prober chuck needs to apply the required force by pushing the wafer against the probe card typically held in place by the structure of the prober. With 200K probes on a 450 mm wafer each requiring 5 gF this is approximately equal to 1 ton (2205 lbF) of applied force. To reduce these force requirements wafer chuck and prober structure, Advantest and JEM have Read the rest of this entry »
June 28, 2012
Click image to download presentation
Here are the highlights from Session Four “New Contactor Technologies and RF PCB Design” of the 22nd annual IEEE
Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
A last minute change to balance the schedule moved my paper “The Road to 450 mm Semiconductor Wafers” from the previous session:
Many believe that Gordon Moore in his famous 1965 paper “The Experts Look Ahead: Cramming More Components onto Integrated Circuits” that has become know as Moore’s Law, said that the number of transistors on a device would double every year (later revised to every two years). He did not say quite that. What he said was Read the rest of this entry »
June 26, 2012
Here are the highlights from Session Three “Probe Potpourri” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 11, 2012.
Larry Levy (FormFactor, Inc.), “Is Parametric Testing About To Enter a Period of Growth and Innovation?”:
Upwards of one thousand facilities perform parametric wafer testing (based on 2009 market data) with over a third of these using obsolete test equipment. There have been no really new testers in several years – Agilent still has their 40xx series and Keithley has their S530 tester. And several companies have exited the market and some companies (including Keithley) are no longer supporting older models of testers. Since parametric testing remains an essential process, this has forced a high number of these facilities to use obsolete equipment or find other approaches. A few companies are going as far as using an Advantest 93000, a significantly more expensive and highly sophisticated digital tester, for parametric test. [Updated to clarify Keithley’s status.]
Parametric testing can be divided into three categories: in-line, end of line (EOL), and quality and reliability. In-line testing is Read the rest of this entry »