IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

Here are the highlights from Session Two – “Optimization / Process Analysis” of the 21st annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Monday June 13, 2011.

Steven Ortiz, Avago, “Probe to Pad Placement Error Correction for Wafer Level S-Parameter Measurements”:

Avago’s film bulk acoustic resonators (FBAR) technology usage is being expanded from filters to include oscillators. The example oscillator discussed operates at a 1.5 GHz resonant frequency with a Quality (Q) factor ranging from one thousand to several thousand and a one year aging specification of less than 25 ppm.

These devices are extremely difficult to test due to their precision and small size (not much larger than the two device pads). The drift specification is the hardest to measure. Since it is generally desirable to have at least 10x measurement capability, the drift measurement requires approximately 2.5 ppm of tester performance, i.e. 3.75 KHz accuracy at 1.5 GHz. They use a GPS locked reference receiver to provide the timing accuracy needed for the test system.

They have determined that a 4 µm shift in probe alignment to the pad results in approximately a 1 ppm shift in the frequency measured. When using a modern prober, probe to pad alignment (PTPA) error of approximately +/- 4.5 µm can be achieved based upon stage accuracy in X, Y & Z axes and motion of the probe. This alignment variation alone would consume almost their entire 2.5 ppm measurement window.

For high frequency devices, typically de-embedding is done once per test fixture or setup to remove the electrical effects of the fixture from the measurement. Measurements of short and open test structures (without a device present) are made to calculate S-parameters which are used to adjust the measurements made on the devices being tested.

To remove the effect of the probe alignment they added eighty copies of short and open structures across every device wafer. They then measure these as they move the probes across the wafer to test the FBAR devices. Using these short and open structures they can calculate new S-parameter to de-embed both the fixturing and the probe misalignment from their measurements.

An experiment to validate this process was done by deliberately misaligning the probes by 25 µm. Without de-embedding less than 1% of the parts pass with the misaligned probes but with de-embedding over 83% pass.

They concluded that even though the FBAR is a very low frequency device, de-embedding substantially improves the repeatability of the measurements and compensates for probe misalignment.

Questions:

  • In consideration of Z axis movement does this create a variation in probe capacitance? The 2:1 over travel ratio will manifest itself as a change in X probe position which will change the measurement result.
  • What is the application of the device? It is used as a higher frequency clock to replace quartz oscillators with multipliers with a significantly smaller package.

Douglas Sottoway, Intel, “Achieving Low-Risk, Volume Manufacturing on Leading Edge Technology Probecards; Definition and Methodology for Implementing a Process Control System”:

Control charts alone are not a process control system (PCS). When used properly they are a key component of a PCS but however engineers require adequate time to explore, investigate, and document signals found in the data.

In addition, four other components are required to make a PCS effective: training, document control, process change control, and management review.

To illustrate the challenges of implementing an effective PCS, examples were shown of missing “signals” in the data and misguided “improvements”. In both cases, production issues become critical as volumes increased and additional production tools were added. Two specific issues identified were:

  • Time based preventative maintenance of tools was not sufficient as it should have also been volume based.
  • Looking at the mean of the data on the control charts missed outliers. A statistic was required that also looked at variation.

Teruyuki Kitagawa, Nomura Plating Co., “Novel Carbonaceous Film with High Electrical Conductivity and Super High Hardness for Semiconductor Test Probes”:

For both test sockets and wafer probes it is necessary to have contacts that provide good electrical contact stability and wear resistance. This need drives requirements for material hardness, low contamination build up, and electrical conductivity.

Their carbonaceous film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000). It is produced by a gas cluster ion beam (GCIB) deposition process. By doping the film with boron (B) they are able to make the carbon conductive (5 x 10E-3 ohm cm) in the range of metal. The film is also “self-cleaning” by having a low surface free energy.

The film quality depends on the angle of deposition which will need to be solved to commercialize the technology. This process has not yet been tested on probes.

Questions:

  • Is the boron doping post deposition? No, the boron is in vacuum chamber during deposition.
  • How thick is the coating? Less than 1 µm so there is no change of the shape of the probe.
  • Any plans to do a n-type film? No, there is not a n-type conductor which can be produced this way. That is why they chose boron (p-type).
  • What are the temperature characteristics? Will it degrade at high temperature probing? During the deposition process the temperature is less than 100 C. [Ed: therefore it is unlikely the probe material will change but this didn’t answer the intended question of what happens to the film at high temperatures.]

One Response to IEEE Semiconductor Wafer Test Workshop – Optimization / Process Analysis – Session Two (Monday)

  1. […] a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher […]

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