IEEE Semiconductor Wafer Test Workshop 2012 – Session 9 (Wednesday)

Semiconductor wafer test workshop swtw sign 500x352

Here are the highlights from Session Nine “Productivity / Cost of Ownership (COO)” of the 22nd annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Wednesday June 13, 2012.

Teruyuki Kitagawa (Nomura Plating, Co., Ltd. – Japan), “Unique Characteristics of the Novel Carbonaceous Film with High Electrical Conductivity and Ultra High Hardness for Semiconductor Test Probes”:

In a follow-up to last year’s presentation, improvements to Nomura’s carbonaceous film were discussed. The film has a much higher hardness (Hv 4000) than palladium (Pd, Hv 350 ~ 400) or even diamond-like carbon (DLC, Hv 1000 ~ 2000) which provides wear resistance and acts as a self cleaning surface. The significant improvement since last year is the electrical conductivity which is now similar to metals. Last year, at 20 gF the contract resistance (Cres) using the carbonaceous film was greater than 2 ohms. Now the Cres is 0.12 ohms which is comparable to 0.10 ohms for gold plated probes. The base material of the film is still carbon with a molecular structure similar to diamond but doped with boron to improve conductivity.

Tests using the improved version of the carbonaceous film shows no visible debris after 30 K touchdowns.  And the film demonstrates higher wear-resistance at temperatures up to 350 °C.

Questions:

  • What is the coefficient of friction? 0.1
  • Will coating probe tip with this film cause it to skid across the surface of the pad? Nomura does not yet have experience with a probe card application. Their experience with tin bumps has not demonstrated any problems.
  • What current has the probes been tested to? And what happens when the temperature is above 350 °C? There is not yet information available on current testing for probes. Above 350 °C the film will oxidize and burn away.
  • What about low temperatures applications at -40 °C? Unfortunately, they do not have a graph of conductivity at low temperates. In their considerable experience using the material at low temperatures, including liquid nitrogen at -180 °C, they have not seen a change in conductivity.
 

Jim Brandes (Multitest), “High Frequency Performance of Modular Wafer Probecards – A Numerical Approach”:

Working with Feinmetall, Multitest has simulated and measured the performance of two different probe card architectures. The first configuration, called S22, is a Feinmetall buckling beam probe head connected to a multi-layer ceramic (MLC) space transformer that is attached to a printed circuit board (PCB). The S23 configuration is similar with the exception that the MLC is connected to a daughter board which is then plugged in to the main PCB (“mother board”) via connectors. One of the goals of the S23 configuration simulation was to determine the performance reduction due to the additional connectors and daughter board PCB.

ANSYS high frequency structural simulator (HFSS) was the primary tool to simulate the various parts of the signal path. Actual measurements were taken which confirm the models. Three optimizations were analyzed for the design:

  • Placing ground vias close to signal vias which dramatically improved frequency response.
  • Back drilling to remove the unnecessary section of the electrical via stub.
  • Switching to high frequency PCB material (with low loss).

All three of these optimizations were deemed to be worthwhile and a new probe card with these changes will be fabricated. The existing designs, S22 and S23, were proven to have sufficient electrical performance up to the giga hertz range. The maximum performance of these designs, including a probe head, on a selected signal is 2 GHz.

Questions:

  • What was the measured performance of the optimized design? Only the unoptimized versions (S22, S23) were built and tested. The optimized version has not yet built.
  • What is the power capacity of these designs? The team discussed power integrity. Since it is becoming an important issue, Multitest and Feinmetall may do some work in that area for a future paper.
 

Samuel Park (IWIN CO.,Ltd. ‐ Korea), “High Volume Low Cost Stamped Spring Probe Development”:

IWIN has developed several spring pins created by a stamping process instead of traditional construction methods using an extruded barrel combined with a wound wire spring. The advantages of stamping include short lead time and lower cost. With a die upwards of 4000 pins per day can be stamped on one machine lowering both lead time and cost.

Three examples of how to form springs by stamping were the basis of one piece and three piece spring pins designs shown in detail. They are able to build spring pins for probing applications with tips as small as 20 µm with a 90 µm “neck” point. 

Mr. Park also discussed the selection process of appropriate materials for each type of spring probe. “Alloy 25” is their primary material since it is low cost with generally good mechanical and electrical parameters. Before stamping they often temper or heat treat the alloy to adjust mechanical strength as needed. They have also used Paliney 7 for some designs since it does not require gold plating however it is a very high cost material.

IWIN is developing probes with an outer diameter less than 200 µm to test devices with 0.3 or 0.4 mm pitch solder balls. And for high speed signal applications, there is a 550 µm spring probe with 250 µm overdrive in development.

(No questions.)

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